Intel is going to start embed custom FPGAs with its own CPU silicon. The FPGA-equipped Xeons will use precisely the same socket and platform as the standard, non-FPGA Xeon CPUs. Nothing will change on the customer front except that perhaps BIOS updates may be required. But the chips should be drop-in compatible. Intel has not stated who provided its integrated FPGA design, but Altera which designs FPGAs is a safe bet because the two companies have worked together on multiple designs in the past. And Altera uses Intel for its manufacturing. Intel Xeon customers can now reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.
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Intel to Offer Custom Xeon CPUs with Embedded FPGA for the Data Center
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(Score: 3, Interesting) by evilviper on Friday June 20 2014, @04:21AM
This sounds like Intel is copying AMD, nearly a decade after the fact.
AMD's Torenza in 2006 offered FPGAs in a CPU socket:
https://en.wikipedia.org/wiki/Torrenza [wikipedia.org]
It was something of a stepping-stone towards AMD's Fusion/APU chips, with an ASIC (GPU) core on the chip.
FPGAs are expensive and slower than ASICs. They only excel at being extremely flexible, so you can develop any kind of processor on a FPGA. For an actual number-crunching workload, I can't imagine why you wouldn't want an ASIC instead.
I suppose it's because Intel doesn't have an ATI group in the wings like AMD does. Intel is far behind in the GPU game, so they can't copy AMD's Fusion and make a product anybody would want. Meanwhile, Fusion CPUs are in-demand for super-computers, and maybe Intel is feeling threatened, and wants something, ANYTHING out there, holding the fort until they can get up to speed.
Hydrogen cyanide is a delicious and necessary part of the human diet.
(Score: 2) by kaszz on Friday June 20 2014, @05:17AM
ASIC is just expensive and inflexible. FPGAs are good at deep pipelines and parallelization which is perfect for really fast data crunching using custom algorithms. Just look out for cumbersome proprietary control configuration software.
If Intel has a problem, the standard approach seems to be adding more megehertzes.. Guess that won't work anymore ;)
AMD could add some on-chip cache though.
(Score: 3, Informative) by me on Friday June 20 2014, @06:39AM
There was a wired article about Bing using FPGA recently.
http://www.wired.com/2014/06/microsoft-fpga/ [wired.com]
Wonder if this is related.
Microsoft's pilot was 1,600-servers.
And as for FPGA verses ASIC, can you really imagine Microsoft swapping chips each time there implementation needs a patch.
(Score: 2) by dbot on Friday June 20 2014, @12:43PM
Yes, instead now they take those critical functions, implement that logic in HDL (verilog/vhdl), create a hardware interface (i.e. memory addresses/dma/interrupts/access semantics), drivers for that interface, and access that driver from their user-land application.
Doesn't sound like much a bother, comparatively.
Realism aside - I'm often thought about just how awesome this would be if mainstream CPUs contained even small FPGAs by default. How awesome would it be to have user-configurable hardware 'by default' on your desktop PC? Even if it was just a small FPGA to start, I think it would open a world of innovation.
(Score: 0) by Anonymous Coward on Friday June 20 2014, @04:09PM
If some malware manages to modify the FPGA code, it would probably be able to make itself super hard to detect and remove.
(Score: 0) by Anonymous Coward on Saturday June 21 2014, @04:56AM
evilviper : sure, you can get better performance and lower prices from ASIC but only if you have enough money & market to play the game at that level...
While even low end FPGAs can implement a dozen simple CPUs and ALUs simultaneously, personally I don't view it as a competitor to GPUs but an alternative for other kinds of acceleration - ie: why execute code general purpose CPU style when you can implement your algorithm directly in gates?
For example, a regex-to-FPGA compiler to build something that can scan text at 50mb/sec, synchronously, and just DMA processed data to the CPU to deal with at it's leisure?
dbot, I concur that this has to be the most dubious kind of marketing bullshit I've seen today... very nicely hedged. While I'm personally very interested in a Xeon with onboard FPGA (messing with Xilinx Zynq which is 2xARM + FPGA) I don't expect to get any acceleration done without writing some code to handle it...