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posted by janrinok on Wednesday August 27 2014, @11:33PM   Printer-friendly
from the I-feel-a-server-upgrade-coming-on dept.

ITworld reports:

Samsung has started producing 64GB DRAM modules for servers based on emerging DDR4 (double-data rate 4) memory using 3D "through silicon via" (TSV) package technology.

The 64GB capacity is the largest for DRAM modules yet, which will improve application performance because data will be kept in memory longer so that bits don't have to be transferred as often between DRAM and other components such as storage.

[...] DDR4 will provide 50 percent more memory bandwidth and 35 percent more power savings than DDR3. Intel is due to release a DDR4-compatible chip called Grantley in early September, which will be used by Lenovo and Dell in servers.

[...] The memory chips in a stack are linked through a connector called TSV, which is emerging as a throughput mechanism for newer memory technologies. TSV is already being used in the emerging HMC (Hybrid Memory Cube) technology from Micron, and will be used by Nvidia in its graphics chips in the coming years.

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  • (Score: 4, Funny) by c0lo on Wednesday August 27 2014, @11:35PM

    by c0lo (156) Subscriber Badge on Wednesday August 27 2014, @11:35PM (#86518) Journal
    You insensitive clods, its only last year I upgraded my workstation.
    --
    https://www.youtube.com/watch?v=aoFiw2jMy-0 https://soylentnews.org/~MichaelDavidCrawford
    • (Score: 2) by kaszz on Wednesday August 27 2014, @11:49PM

      by kaszz (4211) on Wednesday August 27 2014, @11:49PM (#86521) Journal

      Nuke the factory from orbit to restore the order! 2 kByte of RAM should be enough for anyone. It worked for 6502 KIM-1 ;)

      • (Score: 2) by LoRdTAW on Thursday August 28 2014, @03:21PM

        by LoRdTAW (3755) on Thursday August 28 2014, @03:21PM (#86754) Journal

        Pshaw. I had to work on an 8088 student board with 0kB RAM and 2kB EPROM. The only dynamic memory you had were the four registers. And believe it or not you could do a lot of basic stuff with only a few bytes and look up tables.

        • (Score: 2) by kaszz on Thursday August 28 2014, @03:43PM

          by kaszz (4211) on Thursday August 28 2014, @03:43PM (#86762) Journal

          Yeah, computers are really powerful and versatile devices. It's usually up to imagination and time get them do the things you want to.

          Otoh, simulations like SPICE etc.. benefits tremendously from lot's of FPU, GHz and GBytes. Instead of taken days, you get the results in minuts or realtime.

  • (Score: 4, Interesting) by kaszz on Wednesday August 27 2014, @11:46PM

    by kaszz (4211) on Wednesday August 27 2014, @11:46PM (#86519) Journal

    If the new memory takes 0.65 times as much power (per bit?) but uses at least two dies in the same chip package. Then there will be an power increase of at least 1.30 times per chip. So heat is still an issue and the question will be if they have dealt with it appropriately?

    The second issue is the pure density of the storage. When the structure closes in on the size of the sub atomic particles (electrons) used to store. Then you can't use a huge number of those particles to hide defects. And with heavy usage some of them might get stuck. And thus.. have they dealt with this appropriately?

    But this new memory sure looks interesting..

    • (Score: 3, Interesting) by cafebabe on Thursday August 28 2014, @08:10AM

      by cafebabe (894) on Thursday August 28 2014, @08:10AM (#86654) Journal

      Error correction has been used in DRAM since 4Mb chips were available. Additionally, DRAM chips are manufactured with spare rows and a laser is used to bring these rows into service. (A more coarse version of this process occurs with some MMUs, co-processors and multi-core processors.)

      Regarding energy consumption, there have been experimental DRAM designs to multiplex three address lines over one wire. Historically, these designs have been a commercial failure because the primary benefit was to reduce packaging costs at the expense of access time. Regardless, 3D addressing may return if reduces energy consumption.

      --
      1702845791×2
      • (Score: 2) by kaszz on Thursday August 28 2014, @02:13PM

        by kaszz (4211) on Thursday August 28 2014, @02:13PM (#86732) Journal

        How would 3D addressing reduce power usage?

        • (Score: 2) by TK on Thursday August 28 2014, @02:32PM

          by TK (2760) on Thursday August 28 2014, @02:32PM (#86736)

          IANA Electrical Engineer, but my guess is smaller mean distance between the controller and any given position on the module compared to a 2D layout of the same size (GB).

          --
          The fleas have smaller fleas, upon their backs to bite them, and those fleas have lesser fleas, and so ad infinitum
          • (Score: 2) by kaszz on Thursday August 28 2014, @03:06PM

            by kaszz (4211) on Thursday August 28 2014, @03:06PM (#86750) Journal

            So the major part of the power usage isn't on the die but the wires to the CPU/memory controller?

          • (Score: 1, Interesting) by Anonymous Coward on Thursday August 28 2014, @03:24PM

            by Anonymous Coward on Thursday August 28 2014, @03:24PM (#86755)

            I would think that a die shrink with higher density would create higher resistance on-die lowering current.

            • (Score: 2) by kaszz on Friday August 29 2014, @12:52AM

              by kaszz (4211) on Friday August 29 2014, @12:52AM (#86999) Journal

              If the die density increases it should mean less resistance (asfaik) ..?

        • (Score: 3, Interesting) by Random2 on Thursday August 28 2014, @04:18PM

          by Random2 (669) on Thursday August 28 2014, @04:18PM (#86787)
          Wires suck.

          It's been a little while so my details are a bit rusty, but basically the transistor parts have become so small that their effects on overall power consumption become dwarfed in comparison to that lost over the wires. In electrical terms, the wires end up looking like capacitors and resistors, and depending on the size/length can me much larger than the parts they're powering. Traditional circuits tend to not count the wires because of how negligible the capacitance is (unless we're talking power lines) but ICs today are so small that it actually does matter.

          When you've got billions of parts on a die that are all connected together, the wires end up accounting for a significant portion of the overall power draw (especially with DDR, where you've basically got banks and banks of 'really shitty' caps that you're constantly having to recharge). So, doing anything to shorten them is very useful. A quick search for more reading [berkeley.edu]
          --
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        • (Score: 2) by cafebabe on Friday August 29 2014, @12:33AM

          by cafebabe (894) on Friday August 29 2014, @12:33AM (#86995) Journal

          Exposing the internal, rectangular structure of DRAM has been beneficial because it has allowed functionality like burst modes to be implemented. The row and column strobe lines have also had a large amount of overloaded functionality. Most notable is CBR [CAS [Column Address Strobe] Before RAS [Row Address Strobe]] refresh. This allows an otherwise meaningless signal to utilize an internal column counter to recharge one column of DRAM capacitors. Before this signal was implemented, DRAM required external counter circuitry or a suitable microprocessor, like the Z80, to keep count.

          In the 3D case, there is a stack of DRAM chips. However, legacy DRAM controllers are still expecting each bank of DRAM to be a 2D rectangle where the row and column size differs by a power of two, at most. Implementing this legacy interface wastes energy because it requires larger "columns" to be retrieved across multiple chips when retrieval from only one is (probably) required. However, at present, I don't believe that it is possible to specify the real column size.

          If the true 3D structure is exposed, it would also allow new modes of operation to be implemented for the purpose of minimizing energy or maximizing throughput. This is possible because the layers could work independently. However, this will only work fully if accurate statistics are available for each bank of DRAM.

          --
          1702845791×2
  • (Score: 2) by wonkey_monkey on Thursday August 28 2014, @08:23AM

    by wonkey_monkey (279) on Thursday August 28 2014, @08:23AM (#86659) Homepage

    35 percent more power

    Woo!

    savings

    Aww.

    --
    systemd is Roko's Basilisk