The RISC-V project ran the first RISC-V workshop last week, and the content from the workshop is being brought online.
Currently the slide packs are available, with videos to follow. From the blog posting
The videos from the workshop are still being prepared for distribution, but the slides from the talks are now available online at http://riscv.org/workshop-jan2015.html. [Ed Comment: URL intermittent] They represent the most up-to-date information on the Berkeley RISC-V tools and infrastructure.
The RISC-V Project aims to develop an open Instruction Set Architecture (ISA) under a BSD License; from the project homepage:
Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.
The motivation for the project is summarised in The Case for RISC-V (PDF Download) .
Related Stories
An article at Hackerboards is reporting the announcement that fabless semiconductor company SiFive has announced the first embedded SoCs based on the open source RISC-V platform
A VC-backed startup closely associated with the RISC-V project announced the first system-on-chip implementations of the open source RISC-V processor platform. At the RISC-V 4thWorkshop at MIT this week, SiFive announced two embedded SoC families. The Freedom Unleashed family debuts with a 28nm fabricated, Freedom U500 SoC with up to eight 1.6GHz cores that runs Linux, aimed at machine learning, storage, and networking applications. The MCU-like Freedom Everywhere family for Internet of Things starts with a 180nm Freedom E300 model that runs FreeRTOS.
Like RISC-V, both designs are fully open source, but the company also plans to sell finished SoCs with the help of fabrication partner TSMC. The platform will "reverse the industry's prohibitively rising licensing, design and implementation costs," says SiFive.
Although the SiFive announcement talks about the final SoC implementation currently only targets based on standard FPGA based development platforms appear to be available.
This earlier SN article contains more information on the RiscV project and the development of an open Instruction Set Architecture.
(Score: 0) by Anonymous Coward on Friday January 23 2015, @09:53PM
But really, if they were serious they would try to advance a decent architecture that has already had some commercial success, such as MIPS 64.
(Score: 3, Informative) by dbot on Friday January 23 2015, @10:22PM
What's wrong with OpenRISC [opencores.org], doesn't it do all this already? Is it because it's LGPL?
Ah, from Berkeley?
Oh! FTA: "that OpenRISC may have lost momentum"
(Score: 0) by Anonymous Coward on Friday January 23 2015, @11:26PM
Five years from now, if there haven't been any commercial wins for the RISC-V, at least there will have been journal papers, and conferences.
(Score: 1) by GDX on Saturday January 24 2015, @01:10AM
Openrisc is beffy, is actually comparable to a PowerPC while the Risc-V is comparable to an ARM. They had different tradeoff in the design.
(Score: 1) by warcques on Saturday January 24 2015, @01:32AM
There's a brief chart of modern ISA features on page 4 of the "Case for RISC-V" document that Sparc V8 and openRISC don't have (mostly related to quadword stuff).
(Score: 0) by Anonymous Coward on Saturday January 24 2015, @03:35AM
If that's really the reason given by the RISC-V bunch then I think RISC-V is a dead end, since it's likely new features will be needed in the future.
(Score: 3, Informative) by MichaelDavidCrawford on Friday January 23 2015, @10:56PM
The problem is cache control logic is full of hardware patents.
Most ISAs have a way to do this. I regard as least effective, the ARM architecture's ability to preload the L2 cache. In second place is x86_64 as well as I expect the later x86 ISAs ability to declare that one will fill a cache line prior to writing into it, thereby avoiding the need to read from the L2 cache when one writes one's first byte into a cache line.
Most effective - IMHO - are PowerPC's and POWER's - oddly different - abilities to zero-out a cache line with one machine instruction, without hitting the L2 cache.
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(Score: 2) by kaszz on Saturday January 24 2015, @12:09AM
When do they expire?
(Score: 2) by MichaelDavidCrawford on Saturday January 24 2015, @07:54AM
- contents.
Using these techniques can be a little tricky. Commonly it's used for system software and standard libraries. Regular application code would use it however in the hands of newbies of course you would cause memory corruption.
Suppose you are going to write out 32 bytes, aligned with a cache line.
When you write your first byte, before that byte actually gets written, the cache controller will read 32 bytes in from the L2 cache. Sometimes the L2 cache's controller will, prior to that, read 32 bytes in from main memory. Some motherboards have L3 caches.
So you write your first byte, then 31 more bytes. That will, when the cache line does expire, have the effect of overwriting 32 bytes of main memory. Thus it is a complete waste to read in 32 bytes, if you already know what you're going to write out, such as clearing memory in a calloc() implementation, or a newly mapped page in a memory-mapped file, or you are incrementing the allocation in a file and want to avoid a process getting read access to data from the previous content of that new sector.
You don't need this functionality in many places, however the places where you do need it are very frequently called.
You really don't need it at all, strictly speaking, in that your code will be correct however it will be very very slow compared to code that does know how to defeat the cache, and that uses that capacity wisely.
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(Score: 2) by kaszz on Saturday January 24 2015, @01:46PM
So when will the cache control logic patents expire?
(Score: 2) by mtrycz on Friday January 23 2015, @10:59PM
I wasn't aware of this, and this post made me happy.
It's great that open souce is spreding all the way down to the bios, now all the way down to the hardware. The more, the merrier.
Maybe one day, we'll be able to compute on a completely open platform, that anyone with the knowledge (openly available) can produce, live free of proprietary hardware level backdoors, and they lived happily ever after.
Hey, a man can dream!
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(Score: 0) by Anonymous Coward on Friday January 23 2015, @11:22PM
OpenSPARC says hello from 2005.
(Score: 2) by mtrycz on Saturday January 24 2015, @10:01AM
Haven't you read TFS? They're not only doing a spec. They're doing partnerships, workshops and training on this shit, as to actually make it being adopted, also having a roadmap for getting there; it's quite clear from the last link: "Here are the benefits for the users: ...", "Here are the benfits for the producers: ...". Like actually being a real thing in the real world, competing with ARM and shit.
Both you and I can make a spec, but the big thing is adoption.
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(Score: 0) by Anonymous Coward on Saturday January 24 2015, @04:24PM
OpemSPARC is a real thing in the real world and has large companies like Fujitsu behind it.
(Score: 0) by Anonymous Coward on Saturday January 24 2015, @06:51PM
NovelRISC