Xilinx Announces Project Everest: The 7nm FPGA SoC Hybrid
This week Xilinx is making public its latest internal project for the next era of specialized computing. The new product line, called Project Everest in the interim, is based around what Xilinx is calling an ACAP – an Adaptive Compute Acceleration Platform. The idea here is that for both compute and acceleration, particularly in the data center, the hardware has to be as agile as the software. Project Everest will combine Xilinx's highest performing next-generation programmable logic along with application processors, real-time processors, programmable engines, RF, high-speed SerDes, programmable IO, HBM, and a custom network-on-chip. The idea is that space typically devoted to hard blocks in FPGAs (such as memory controllers) are now optimized on chip, leaving more programmable silicon for the compute and adaptability. Project Everest is one of the Three Big Trends as identified by Xilinx's new CEO, Victor Peng.
[...] Xilinx's ACAP portfolio will be initiated with TSMC's 7nm manufacturing process, with the first tapeouts due in late 2018. Xilinx states that Project Everest has been a monumental internal effort, taking 4-5 years and 1500 engineers already, with over $1b in R&D costs. The final big chips are expected to weigh in at 50 billion transistors, with a mix of monolithic and interposer designs based on configurations.
Today's announcement is more of a teaser than anything else – the diagram above is about the limit to which that Xilinx will talk about features and the product portfolio. The value of the ACAP, according to Xilinx, will be its feature set and millisecond-level configurability. For a server on the edge, for example, an ACAP can use both the programmable logic elements for millisecond bitstream reconfiguration of different processes along with the application processors for general logic or the programmable engines as ASIC-level acceleration. This can lead to, among other things, different AI acceleration techniques and 5G RF manageability by multiple containers/VMs on a single ACAP. The overriding idea is that the ACAP can apply dynamic optimization for workloads, with Xilinx citing a 10-100x speedup over CPUs and more use cases than GPUs or ASICs as a fundamental value to the new hardware, built through software and hardware programmability. Xilinx also stated that the RF will have four times the bandwidth of current 16nm radios, leveraging 16x16 800 MHz radios.
Also at The Register and The Next Platform.
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AMD Is Gearing up To Acquire Xilinx (XLNX) for $30 Billion
AMD, a major player in the semiconductor sphere, is gearing up to acquire Xilinx for $30 billion, thereby, providing an impetus to the ongoing consolidation wave in the industry.
According to the sources quoted by [The] Wall Street Journal, AMD and Xilinx are currently in an advanced stage of negotiation, with a potential deal emerging as early as next week.
Bear in mind that Xilinx manufactures programmable chips for wireless networks and its acquisition will provide AMD a solid foothold in an industry that is currently in flux. With carriers injecting billions of dollars in the telecommunication sphere in order to expand the coverage of the next-gen 5G wireless network, Xilinx has become an important node in this endeavor.
However, the deal may be rejected:
The details of the deal revealed yesterday suggest that AMD is interested in paying up to $20 billion for acquiring Xilinx. This marks a roughly 20% premium over the acquisition target's closing share price yesterday. Xilinx is responsible for manufacturing communications and processing products, and it specializes in semiconductors dubbed as field-programmable gate arrays (FPGAs). These differ from application-specific integrated circuits (ASICs, such as a microprocessor) by allowing use-customization after manufacturing.
Following the revelation, analysts from Citi Group, Wedbush, Citigroup and CNBC have pitched in their opinions about the affair. The majority of the analysts are skeptical of the deal's outcome as they either believe that no synergies exist between AMD and Xilinx, or that Xilinx management will likely reject the deal.
The Radeon designer's primary objective behind the move is likely to be the intention of competing with Intel Corporation in the FPGA sector. Due to the nature of FPGAs, they are often found in a large array of tech products. Such products cover applications such as neural networks, aerospace, automotive, finance, data centers and wireless and wired communications.
Also at Phoronix.
Related: Xilinx 7nm FPGA SoC
Xilinx Alveo U280 Launched, Possibly with AMD EPYC CCIX Support
(Score: 1, Insightful) by Anonymous Coward on Wednesday March 21 2018, @02:54AM (3 children)
Not only are there tools proprietary, but the software they force you to use is egregiously bad.
(Score: 0) by Anonymous Coward on Wednesday March 21 2018, @09:13AM
What, still?
Last time I used their stuff was 18-19 years ago (I jumped careers at about that time, and have had no need to look at their stuff since), I remember it being quite nasty to use back then...and expensive. Mind you, I should probably also mention that the idiots I worked for at the time had this crazy idea about using Orcad as the 'front end' (as they put it) for driving it.
(Score: 0) by Anonymous Coward on Wednesday March 21 2018, @06:15PM (1 child)
No slaveware announcements should be posted on soylentnews.
(Score: 2) by bob_super on Wednesday March 21 2018, @06:43PM
Feel free to help the world by starting your own Open version of the FPGA tools. While bloated to some extent, the Xilinx tools are a 20GB install to support one family of parts (40G if you take the whole thing). And the next family will not work until you write specific code to target the new hard cores.
It ain't "slaveware", moron. The company provides the tools you need to use the parts they sell. While the tools are far from perfect, nobody else has the time or business case to provide an alternative. If you don't like that, you can try to buy a chip from Intel and an Open version of those tools.
(Score: 2) by JoeMerchant on Wednesday March 21 2018, @03:15AM (5 children)
Sure, they're configurable and fast, but the applications where that configurability matters enough to overcome the cost and power consumption are very few and far between.
As noted by AC, if they're still in the Eclipse toolchain I have no desire whatsoever to re-engage with them. Nothing against Eclipse, just their butchering of it.
🌻🌻 [google.com]
(Score: 2) by RS3 on Wednesday March 21 2018, @03:39AM (4 children)
Yeah, I always thought of them as prototyping only. Every now and then I see them in a product and I'm surprised. I've never used a Xilinx chip in a design, a few small gate arrays, but I don't do much digital design lately, not at that complexity anyway.
(Score: 3, Informative) by bob_super on Wednesday March 21 2018, @05:49AM (3 children)
I've been designing with Xilinx chips for 19 years.
If you have the volumes (consumer products), and fixed standards, an ASIC will end up cheaper.
If you only need limited real-time processing, a processor will do the job.
But there are quite a few billion dollars to be made selling the stuff that's in between (Intel bought Altera for what, $14B?).
Line rate HD/4K video processing, really fast networking (50G, 100G, 400G, multiple channels), High-Frequency Trading, optimized coprocessing... That's a big niche, with nice fat margins, and pretty well-paid engineers.
(Score: 2) by JoeMerchant on Wednesday March 21 2018, @01:27PM
Bleeding edge video processing is one place where FPGAs are convenient, especially limited volume essentially proof of concept (often military) applications.
The HFT guys could use ASICs if they weren't all trying to out-clever the next guy.
The place I was at was seriously struggling to justify it - it looked great on the sales brochure, but profitable applications were seriously lacking.
🌻🌻 [google.com]
(Score: 2) by RS3 on Thursday March 22 2018, @01:18AM (1 child)
Crypto-currency "mining" too I would assume?
How about GPUs for all the stuff you mentioned?
(Score: 3, Informative) by bob_super on Thursday March 22 2018, @01:46AM
GPUs almost always talk to a host via PCIe. FPGAs typically get their data straight from the pipe (Video, Ethernet, fibre channel...), saving the whole CPU loop, helping tremendously in real-time applications.
Also, GPUs are fundamentally an array of little processors specialized in crunching parallel math instructions, with some controls and loops, and uploading results back to a memory. They're the best at what they do. FPGAs, on the other hand, crunch data at lower clocks, but pretty much every single clock tick (some blocks have minor latencies), and can merge and split memories and datastreams in real time with high precision, creating standard-complaint streams and other wholistic behaviors which a CPU or GPU is ill-fitted for.
It's hard to summarize in one post. You can't crunch the content of a 400Gig-E pipe with a GPU. That doesn't takes an insane FPGA (the biggest can do multiple 400GE), and it will do it within a tolerable thermal envelope, though for a pretty high price (which typically doesn't matter if you have to crunch a 400G pipe).
Fundamentally, it's the difference between sequential and heavily parallelized programming (CPU/GPU) versus concurrent programming (FPGA/ASIC). Every piece of data in the FPGA could be processed with every clock cycle (typically not, but every flop's input is evaluated at every tick). A CPU/GPU will grab one chunk of data (one register, maybe a SIMD), move it to process, then push it back, then grab the next one, heavily pipelined, but still nowhere near the less-flexible super-efficiency of an ASIC dataflow (and an ASIC is just an optimized frozen FPGA).
(Score: 0) by Anonymous Coward on Wednesday March 21 2018, @05:37AM
This stuff is going to be available only to the most spendy customers for quite some time, I expect. Xilinx loves to make a big splash but you either can't afford it or can't get it.
(Score: 2) by bootsy on Wednesday March 21 2018, @11:09AM
Xilinix stuff is used in high frequency trading as the data comes in faster than the clock cycle of the fastest Intel processor.
Quite a few Hedge Funds implement their algos directly on Xilinx, with some of the sneakier ones doing things like implementing a partial TCP/IP stack so they can do enough processing to get the data they need from a FIX message without having to do all the full decoding. I think the Algo coders benefit from the fact the Xilinx is a pig to program for as it means there are hardly any people doing it and so they get paid rather well.
Chord Electronics are using Xilinx chips to implement a custom DAC which measures amongst the best ever made in terms of signal to noise and dynamic range.
The custom ASIC vs FPGA thing is interesting. We evaluated hardware accelerated zip compression and we saw both ASIC and FPGA approaches.
I've seen some ultra fast network interface cards being implemented using Xilinx as well. I'd post links to the vendors but its such a niche space is ends up looking like I am advertising. If anyone is interested then reply asking for them and I'll post them.