PCI Express Bandwidth to Be Doubled Again: PCIe 6.0 Announced, Spec to Land in 2021
When the PCI Special Interest Group (PCI-SIG) first announced PCIe 4.0 a few years back, the group made it clear that they were not just going to make up for lost time after PCI 3.0, but that they were going to accelerate their development schedule to beat their old cadence. Since then the group has launched the final versions of the 4.0 and 5.0 specifications, and now with 5.0 only weeks old, the group is announcing today that they are already hard at work on the next version of the PCIe specification, PCIe 6.0. True to PCIe development iteration, the forthcoming standard will once again double the bandwidth of a PCIe slot – a x16 slot will now be able to hit a staggering 128GB/sec – with the group expecting to finalize the standard in 2021.
[...] PCIe 6.0, in turn, is easily the most important/most disruptive update to the PCIe standard since PCIe 3.0 almost a decade ago. To be sure, PCIe 6.0 remains backwards compatible with the 5 versions that have preceded it, and PCIe slots aren't going anywhere. But with PCIe 4.0 & 5.0 already resulting in very tight signal requirements that have resulted in ever shorter trace length limits, simply doubling the transfer rate yet again isn't necessarily the best way to go. Instead, the PCI-SIG is going to upend the signaling technology entirely, moving from the Non-Return-to-Zero (NRZ) tech used since the beginning, and to Pulse-Amplitude Modulation 4 (PAM4).
[...] PCIe 6.0 will be able to reach anywhere between ~8GB/sec for a x1 slot up to ~128GB/sec for a x16 slot (e.g. accelerator/video card). For comparison's sake, 8GB/sec is as much bandwidth as a PCIe 2.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
PCIe 5.0 Specification Finalized (yes, that was 3 weeks ago)
Related Stories
http://www.tomshardware.com/news/pcie-4.0-5.0-pci-sig-specfication,35325.html
PCIe is the ubiquitous engine that pulls a big part of the computing locomotive down the track—it touches nearly every device in your computer. As such, it is the linchpin for the development of many other technologies, such as storage, networking, GPUs, chipsets, and many other devices. Considering its importance, it isn't surprising to find the PCI-SIG with 750 members worldwide. Unfortunately, large organizations tend to move slowly, and PCIe 4.0 is undoubtedly late to market. PCIe 3.0 debuted in 2010 within the normal four-year cadence, but PCIe 4.0 isn't projected to land in significant quantities until the end of 2017—a seven-year gap.
PCI-SIG representatives attributed part of the delay to industry stagnation. The PCIe 3.0 interface was sufficient for storage, networking, graphics cards, and other devices, for the first several years after its introduction. Over the last two years, a sudden wellspring of innovation exposed PCIe 3.0's throughput deficiencies. Artificial intelligence craves increased GPU throughput, storage devices are migrating to the PCIe bus with the NVMe protocol, and as a result, networking suddenly has an insatiable appetite for more bandwidth.
The industry needs PCIe 4.0 to land soon, and PCI-SIG assures us it will ratify the new specification by the end of 2017. The sluggish ratification process hasn't hampered adoption entirely, though. Several IP vendors already offer 16GT/s controllers, and many vendors have already implemented PCIe 4.0 PHYs into their next-generation products. These companies are plowing ahead with the 0.9 revision of the specification, whereas the final ratified spec debuts at 1.0. PCI-SIG says it is accelerating the development and feedback processes, along with simplifying early specification revisions, in a bid to reduce time to market for future specifications. PCI-SIG indicates that PCIe 4.0 will be a short-lived specification because the organization has fast-tracked PCIe 5.0 for final release in 2019.
[...] AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
The industry has been stuck on PCIe 3.0 for roughly seven years, and even though the first support for PCIe 4.0 on the desktop will land soon in AMD's third-gen Ryzen chips and the first PCIe 4.0 SSDs just cropped up, the industry is already adopting PCIe 5.0. The new standard doubles throughput over PCIe 4.0, yielding a data rate of 32 GT/s.
Today PCI-SIG, the organization that defines PCIe standards, announced that it ratified Version 0.9 of the PCI Express 5.0 specification, signaling that end devices will come to market in the near future. (Companies design end devices as early as revision 0.4 and often launch with 0.9.)
[...] PCIe 4.0 brings 64GBps of throughput, while PCIe 5.0 will double that to 128GBps. Both revisions still use the 128b/130b encoding scheme that debuted with PCIe 3.0. PCI-SIG representatives said they are satisfied with the 20% reduction in overhead facilitated by the 128b/130b encoding, and further encoding refinements to reduce the current 1.5% overhead are subject to a diminishing point of returns.
PCIe 5.0 also brings other features, like electrical changes to improve signal integrity, backward-compatible CEM connectors for add-in cards, and backward compatibility with previous versions of PCIe. The PCI-SIG also designed the new standard to reduce latency and tolerate higher signal loss for long-reach applications.
Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec
Following the long gap after the release of PCI Express 3.0 in 2010, the PCI Special Interest Group (PCI-SIG) set about a plan to speed up the development and release of successive PCIe standards. Following this plan, in late 2017 the group released PCIe 4.0, which doubled PCIe 3.0's bandwidth. Now less than two years after PCIe 4.0 – and with the first hardware for that standard just landing now – the group is back again with the release of the PCIe 5.0 specification, which once again doubles the amount of bandwidth available over a PCI Express link.
Built on top of the PCIe 4.0 standard, the PCIe 5.0 standard is a relatively straightforward extension of 4.0. The latest standard doubles the transfer rate once again, which now reaches 32 GigaTransfers/second. Which, for practical purposes, means PCIe slots can now reach anywhere between ~4GB/sec for a x1 slot up to ~64GB/sec for a x16 slot. For comparison's sake, 4GB/sec is as much bandwidth as a PCIe 1.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
Previously:
PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
Obligatory xkcd
Micron Spills on GDDR6X: PAM4 Signaling For Higher Rates, Coming to NVIDIA's RTX 3090
It would seem that Micron this morning has accidentally spilled the beans on the future of graphics card memory technologies – and outed one of NVIDIA's next-generation RTX video cards in the process. In a technical brief that was posted to their website, dubbed "The Demand for Ultra-Bandwidth Solutions", Micron detailed their portfolio of high-bandwidth memory technologies and the market needs for them. Included in this brief was information on the previously-unannounced GDDR6X memory technology, as well as some information on what seems to be the first card to use it, NVIDIA's GeForce RTX 3090.
[...] At any rate, as this is a market overview rather than a technical deep dive, the details on GDDR6X are slim. The document links to another, still-unpublished document, "Doubling I/O Performance with PAM4: Micron Innovates GDDR6X to Accelerate Graphics Memory", that would presumably contain further details on GDDR6X. None the less, even this high-level overview gives us a basic idea of what Micron has in store for later this year.
The key innovation for GDDR6X appears to be that Micron is moving from using POD135 coding on the memory bus – a binary (two state) coding format – to four state coding in the form of Pulse-Amplitude Modulation 4 (PAM4). In short, Micron would be doubling the number of signal states in the GDDR6X memory bus, allowing it to transmit twice as much data per clock.
[...] According to Micron's brief, they're expecting to get GDDR6X to 21Gbps/pin, at least to start with. This is a far cry from doubling GDDR6's existing 16Gbps/pin rate, but it's also a data rate that would be grounded in the limitations of PAM4 and DRAM. PAM4 itself is easier to achieve than binary coding at the same total data rate, but having to accurately determine four states instead of two is conversely a harder task. So a smaller jump isn't too surprising.
The leaked Ampere-based RTX 3090 seems to be Nvidia's attempt to compete with AMD's upcoming RDNA2 ("Big Navi") GPUs without lowering the price of the usual high-end "Titan" GPU (Titan RTX launched at $2,499). Here are some of the latest leaks for the RTX 30 "Ampere" GPU lineup.
Previously: GDDR5X Standard Finalized by JEDEC
SK Hynix to Begin Shipping GDDR6 Memory in Early 2018
Samsung Announces Mass Production of GDDR6 SDRAM
Related: PCIe 6.0 Announced for 2021: Doubles Bandwidth Yet Again (uses PAM4)
(Score: 0) by Anonymous Coward on Wednesday June 19 2019, @03:27PM (3 children)
Are there energy/temperature/price trade offs vs implementing PCIe 4.0, 5.0, or 6.0? Eg, are we going to see laptops and low end workstations with PCIe 4.0, gaming/pro PCs with PCIe 5.0, while HEDT and servers have PCIe 6.0?
Obviously the motherboards will only support a specific PCIe version, but how about CPUs?
(Score: 3, Interesting) by takyon on Wednesday June 19 2019, @03:37PM (2 children)
The price is expected to be high. Energy consumption may be higher. Physical limits are appearing.
I have no idea about laptops with 4.0. AMD's laptop chips lag behind desktop. AMD's new products support PCIe 4.0 although support may be limited to newer motherboards. Intel has said it will support PCIe 5.0 in 2021. We'll see about 6.0.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 5, Insightful) by bob_super on Wednesday June 19 2019, @05:06PM (1 child)
It might be the opposite.
4.0 is 16Gb/s/lane, which is pretty easy to do in a laptop where you control the traces. In a desktop with a slot, that's already trickier but not daunting. Do not buy 4.0 extension cards made by cheap morons who don't understand signal integrity, and plug your cards in properly, so the EQs can do they job.
Power is irrelevant at 16G in 14 or less nm. You could get 128 transceivers cooking in an FPGA a while back at 22nm, and their power was meh compared to the rest of the logic processing that data.
5.0 is 32Gb/s/lane. 4 years ago, I know first-hand that it was still hard to do on a fully-controlled PCB, because the weave of the material can even come into play at those frequencies. But it worked with careful design. I'd trust that most laptop manufacturers will have it figured out by now. Again, the discontinuity of adding the slot in a desktop, the longer traces, and the quality of the extension card you plug it, make me think lots of people will have issues. They might silently run at a lower speed (not sure how well their OS will tell them), or there might be lots of RMAs.
A 16nm Xilinx FPGA power-estimates at 625mW per lane per end running 32G 128b/130b. Even counting an ASIC will cut that in half, that's a bit much for an ultrabook today. On the other hand, the thin-and-light laptops are not the ones sporting a discrete GPU with x16 connections, so limited use of 5.0 should be acceptable, and 7nm chips will cut the power down again.
6.0, 64Gb/s/lane with PAM4 ? Probably limited to very few performance-critical lanes for a while, and the idea of slots is pretty scary.
(Score: 2) by takyon on Wednesday June 19 2019, @05:18PM
I just meant that AMD's laptop chips are released later than their desktop chips. Latest rumor [notebookcheck.net] is that it could come out in Q4 which is earlier than usual, but we still know nothing about core counts, use of chiplets, if it will use Vega or Navi graphics, etc.
Nobody here will be seeing PCIe 6.0 anytime soon unless it's at work.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by Booga1 on Wednesday June 19 2019, @04:39PM (1 child)
PCIe 4.0 finally hit after being delayed year after year.
They can paper-launch anything, but I'm done waiting on them. Let me know when they've got end-user products undergoing final testing.
(Score: 2) by takyon on Wednesday June 19 2019, @04:50PM
I think the need for PCIe 4.0 and faster revisions wasn't as urgent in the past. Now we have ultra fast SSDs and 3D XPoint along with bandwidth-hungry GPUs and other coprocessors [wikichip.org]. So PCI-SIG is preparing these at a faster pace to match the needs of vendors.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 4, Informative) by Rupert Pupnick on Wednesday June 19 2019, @05:08PM
Typical PCB losses go up in proportion to the sum of both f (dielectric loss) and sqrt(f) (skin effect) terms, so doubling the operating frequency more than doubles the loss per unit distance, which after a while gets truly oppressive for NRZ. Highest signaling rate I’ve seen (2017, in case you were wondering) for electrical interfaces that service OTN is about 28 Gb/s per differential pair. To get to 56 Gb/s these standards are also going to PAM4.
When you use 4 level signaling, you need a better signal to noise ratio to get the same BER performance. This will result in even more prescriptive routing rules for designers that will undoubtedly use up more board resources. Also, since noise sensitivity is going up, designers may be in for some surprises because real PCB noise simulations are pretty much non existent.
Probably a significant cost/yield impact on the silicon, too. Receiver complexity is significantly higher than a regular old NRZ macro.
(Score: 2) by EvilSS on Wednesday June 19 2019, @06:22PM (1 child)
(Score: 1, Funny) by Anonymous Coward on Wednesday June 19 2019, @07:01PM
Just go into stasis for 6 years. Then a 50 Watt GPU will have the performance of the old 200 Watt GPUs, and so on.