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posted by janrinok on Saturday November 07 2015, @03:12AM   Printer-friendly
from the 8=4 dept.

In 2011 AMD released the Bulldozer architecture, with a somewhat untraditional implementation of the "multicore" technology. Now, 4 years later, they are sued for false advertising, fraud and other "criminal activities". From TFA:

In claiming that its new Bulldozer CPU had "8-cores," which means it can perform eight calculations simultaneously, AMD allegedly tricked consumers into buying its Bulldozer processors by overstating the number of cores contained in the chips. Dickey alleges the Bulldozer chips functionally have only four cores—not eight, as advertised.


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  • (Score: 5, Informative) by gman003 on Saturday November 07 2015, @04:05AM

    by gman003 (4155) on Saturday November 07 2015, @04:05AM (#259813)

    Modern CPU cores ("modern" in this case meaning Pentium Pro / K5 and later) are complicated beasts. Within each core, you have an instruction decoder (which can decode multiple instructions per clock), a few buffers between decode and execute (for instruction reordering), and then a number of execution units, each of which can process only a subset of all possible instructions. Multiple execution units can process instructions simultaneously - originally this was so you could do a store/load while doing an FDIV, but now CPUs will have multiple copies of the same execution unit so you can do several at once. As an extreme example, a current Intel core can do four integer multiplies and four load/stores at once.

    While all that horsepower was originally added to speed up a single execution thread, if you have a bad instruction mix (or just stall on memory reads) it makes more sense to allow multiple execution threads to share the core (this is separate from OS-level multithreading, which simply time-slices the CPU to allow different processes full access to the core). Intel was the first to do this (at least in x86 land*), starting in the Pentium 4 era. Their trademarked term for it is "HyperThreading" - they advertise each "core" as merely a core, and list twice the number of "threads" on chips with it enabled. Since they get about a 20-40% performance boost, that's reasonable.

    AMD did not implement simultaneous multithreading until Bulldozer**. They really came at it from a different angle - instead of growing one core, they were trying to shrink their cores (so as to pack more onto one chip), and decided to have some execution units "shared" between two cores - the two-"core" component being named a "module". Each module has two decoders (capable of two instructions per clock), four integer units, two load units, two store units, and two floating-point SIMD units (which chain together for 256-bit SIMD). They also have two separate L1 caches and a shared L2 cache (the L3 cache is shared between all modules in one chip).

    On the face of it, each Excavator"module" is about on part with a Haswell "core". Same decode rate, about the same execution rate. Excavator is significantly more limited in using its full resources for a single process, though it does take up slightly less die space (or would, if they were on the same process node, but AMD fell way behind on that... they're still putting out 28nm chips while Intel is at 14nm****).

    I can't decide if this lawsuit is valid or not. AMD definitely chose their terminology with marketing in mind. The thing they call a "core" is a pretty pathetic core for a desktop CPU - it's about equal to a core in an Apple iPad chip. But on the other hand, it does make sense to call it a "core", given the history. You could just as well argue that Intel's "core" is really two cores. I'm pretty sure it's not enough to sue over, at any rate, but you'll have to find someone else to explain advertising law to you.

    * This stuff was used long before on mainframes. Current IBM processors actually do four-way multithreading, running four threads on a single core at once. Oracle's SPARC does a different thing - each "core" processes eight threads, but in lockstep, processing one instruction from each in turn, as a way to reduce the hit from cache misses.

    ** Quick primer on CPU codenames: Intel throws a new uarch out every year, but they haven't really changed their general design since Nehalem in 2009, they've just been slowly growing them while working mainly on lowering idle power draw. I'm using Haswell as my reference point - there's the newer Broadwell and Skylake, but they haven't unveiled any really deep architectural details. AMD updates far less often, and their last big update was Bulldozer. They followed this with Piledriver, Steamroller and now Excavator. AMD is currently working on a ground-up new design, called Zen, expected sometime next year.

    *** Oh, and both Intel and AMD have a low-power architecture as well. Intel has Silvermont, aimed at bottom-end netbooks and top-end smartphones, while AMD has Bobcat/Jaguar/Puma, which is designed more for the laptop market (and was also used in the PS4 and Xb1 game consoles... for some reason). AMD is also working on an ARM64 processor design, aimed at the server market, called "K12", and Intel has a third uarch designed for the embedded market.

    **** Don't take the process node names too literally. They measure only the smallest feature - with FinFET in particular, transistors are more rectangular than square, and the longer dimension hasn't been shrinking as much, so Intel doesn't have nearly a 4x lead in transistor density.

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