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Intel's Knights-branded Xeon Phi chips remain the most familiar "many-core" accelerators or coprocessors. However, another name has emerged recently: PEZY, whose 1,024-core chips were used in the top 3 most efficient supercomputers. Tom's Hardware reports that PEZY's next generation of chips will boost the core count to 4,096 and integrate Imagination's 64-bit MIPS Warrior CPU onto a system-on-a-chip:
PEZY Computing, a Japanese firm that makes the top three most efficient supercomputers in the world, according to the Green500 list, announced that it will integrate Imagination's highly efficient 64-bit I6400 CPUs into its many-core architecture.
The PEZY SC-2 will be PEZY's next-generation system, which will increase the 1024 core count of the first generation PEZY SC to 4096 cores, or four times more. PEZY's many-core accelerator has been combined with Intel CPUs from top supercomputers to significantly increase their efficiency for computing tasks. For instance, the Shoubo supercomputer, which uses Haswell XEON CPUs and PEZY SC many-core accelerators, was able to break the world record with 7 GFLOPS/W performance.
In the November edition of Green500, the top 23 supercomputers used a heterogeneous architecture with many-core accelerators. In the updated June edition of this year, that number increased by 40 percent, and now the top 32 supercomputers are using many-core accelerators. These supercomputers all use accelerators from AMD, Intel, Nvidia and PEZY. The current top 3 supercomputers are manufactured by PEZY Computing and Exascaler Inc, and include Haswell or Ivy Bridge Xeons as well as PEZY many-core accelerators.
Presumably the integration of the MIPS CPU could allow relatively power-hungry Intel Xeons to be ditched entirely.
Previously: MIPS Strikes Back: 64-bit Warrior I6400 Arrives
(Score: 1, Funny) by Anonymous Coward on Wednesday November 18 2015, @03:33AM
Yes, but will it run Irix? If not, who cares?
(Score: 4, Informative) by TheRaven on Wednesday November 18 2015, @09:21AM
For a supercomputer, this is probably fine. MIPS64r6 is a much nicer ISA than any previous MIPS and people who are spending tens of millions of dollars on a computer can probably be expected to recompile their code.
sudo mod me up
(Score: 2) by FatPhil on Wednesday November 18 2015, @06:02PM
That's a bit weird. For simplicity, did compiler writers just stuff the same instruction in the branch delay slot and the next address after the non-taken branch? (Namely a bit of the loop that should always be performed.) Sure, that's code bloat, but it's simple (it makes it behave more like a traditional branch delay slot, it's just you need 2 copies of the instruction).
However, any good MIPS news is good news. I'm a rabid anti-x86-ite! Shame that it's now in the hands of the bodgers at IMG, when I used to work alongside them they were useless f[rest of post elided, to keep blood pressure low]
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 2) by TheRaven on Wednesday November 18 2015, @06:49PM
That's a bit weird. For simplicity, did compiler writers just stuff the same instruction in the branch delay slot and the next address after the non-taken branch?
Typically, you'll just hoist one instruction from the branch target into the delay slot. The idea was that it's easier to find an instruction to stuff in the delay slot if it only has to be from one target, not something that's useful for both targets. If the branch isn't taken, then you have to cancel that instruction, but no one cares because you're in the slow path (you've not taken a likely branch).
I'm a rabid anti-x86-ite!
If you're looking for a fun non-x86 platform, Cavium's ThunderX is really nice. They've been giving a few away for open source projects to play with.
sudo mod me up
(Score: 2) by FatPhil on Wednesday November 18 2015, @08:34PM
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves