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Submitted via IRC for TheMightyBuzzard
After more than 50 years of miniaturization, the transistor could stop shrinking in just five years. That is the prediction of the 2015 International Technology Roadmap for Semiconductors, which was officially released earlier this month.
After 2021, the report forecasts, it will no longer be economically desirable for companies to continue to shrink the dimensions of transistors in microprocessors. Instead, chip manufacturers will turn to other means of boosting density, namely turning the transistor from a horizontal to a vertical geometry and building multiple layers of circuitry, one on top of another.
For some, this change will likely be interpreted as another death knell for Moore's Law, the repeated doubling of transistor densities that has given us the extraordinarily capable computers we have today. Compounding the drama is the fact that this is the last ITRS roadmap, the end to a more-than-20-year-old coordinated planning effort that began in the United States and was then expanded to include the rest of the world.
[...]
This final ITRS report is titled ITRS 2.0. The name reflects the idea that improvements in computing are no longer driven from the bottom-up, by tinier switches and denser or faster memories. Instead, it takes a more top-down approach, focusing on the applications that now drive chip design, such as data centers, the Internet of Things, and mobile gadgets.
(Score: 2) by takyon on Monday July 25 2016, @07:17PM
That will be a neat trick in and of itself. Chips with one or more core per layer and dozens or more layers could have 1-2 orders of magnitude greater parallel performance. This could require nanotubes, SiGe, or other technologies to solve the heat problem.
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(Score: 2) by bob_super on Monday July 25 2016, @08:57PM
Stacking separate chips does help with yields, reducing costs, but the stacking process isn't cheap yet, so it make sense for expensive stuff.
When it comes to heat, making channels for the heat to flow through is costly in real estate, and only good for low-power chips. We can't sandwich things if every layer needs a >20W power feed and the same 20W extracted out as heat.
Stacking memory on high-power chips makes sense, but only if the much cheaper solution of putting it next door on the substrate is really a non-starter...
That leaves few worthwhile applications form stacking, until the tech improves...
(Score: 3, Informative) by takyon on Monday July 25 2016, @09:41PM
Vertical NAND and HBM on top of CPUs are nice, but the existing stacking process is not going to work for CPUs. It's possible that post-CMOS technologies will be able to drastically reduce power consumption and leakage, to the point where 3D/layered CPUs could be feasible. Stuff like these:
http://spectrum.ieee.org/semiconductors/devices/the-tunneling-transistor [ieee.org]
http://phys.org/news/2013-06-harnessing-potential-quantum-tunneling-transistors.html [phys.org]
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(Score: 2) by TheRaven on Tuesday July 26 2016, @10:27AM
Stacking separate chips does help with yields, reducing costs, but the stacking process isn't cheap yet, so it make sense for expensive stuff.
The other reason for stacking is that it makes it easy to combine different technologies. Most mobile devices have LPDDR stacked on top of the SoC die. It wouldn't make sense to put them on the same die, because the technology used to manufacture DRAM is very different to that used to manufacture processors (something that is causing issues for people like IBM and HP, who want to move some compute closer to the DRAM).
sudo mod me up
(Score: 2) by bob_super on Tuesday July 26 2016, @04:24PM
The problem with "different" techs is that they have to be similar enough to be stacked. Thru-Silicon Vias are tiny, so you don't want any difference in thermal expansion between the layers