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posted by martyb on Sunday July 31 2016, @02:19AM   Printer-friendly
from the memories... dept.

Nvidia was sued over incorrect specifications published for its GeForce GTX 970 GPU. The cards had less render output units than originally stated, and instead of 4 GB of VRAM, they had 3.5 GB and an additional 512 MB in a separate partition, (theoretically) leading to performance issues. Nvidia has agreed to a proposed settlement that would allow U.S. owners of the GTX 970 to claim $30. The settlement has not been approved by the court yet:

Word comes from Top Class Actions (via The Tech Report) that NVIDIA will soon be settling a series of proposed class action lawsuits brought against the company regarding the GeForce GTX 970. Under the preliminary settlement, United States residents who purchased GeForce GTX 970 cards would be able to claim a $30 settlement in return for dropping further litigation against the company. With the GTX 970 having launched at $329, this amounts to a de facto 9% rebate on the card.

The class action suits in question were brought against the company almost immediately after NVIDIA made the important (and more than a bit painful) disclosure that the initially published specifications for the GTX 970 were wrong. Specifically, that the card had an unusual memory crossbar organization where one ROP/L2 partition was disabled, giving the card only 56 ROPs instead of 64. Furthermore, this meant that the last 512MB of the standard 4GB of VRAM could not be accessed in a contiguous manner, impacting how it could be used.

Never Settle!


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  • (Score: 2) by shortscreen on Sunday July 31 2016, @09:13AM

    by shortscreen (2252) on Sunday July 31 2016, @09:13AM (#382218) Journal

    Does anyone know how these oddball bus widths are handled by the GPU? I know they've been around for a while (since the 8800 IIRC) but I have not seen an explanation yet. Is memory still organized in a linear fashion or is it interleaved somehow? How do they avoid misaligned accesses? Is the cache line size dependant on the bus width?

    I heard something about the GPU having multiple memory controllers... does that mean they have separate address buses to each chip or bank of chips?

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