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takyon writes:

AMD unexpectedly (page 4) released details about its upcoming Zen CPU microarchitecture:

AMD hosted an offsite invitation-only briefing during IDF to unveil the company's new Zen processor core microarchitecture, which will initially come to market in its Summit Ridge desktop CPUs. [...] AMD's original goal was to increase Zen's IPC (Instructions Per Cycle) performance by 40 percent compared to the previous-generation Excavator core. According to the company, it achieved its goals. AMD also noted that the company focused on providing power efficiency gains in tandem with the performance improvements, which is the key attribute that will allow the Zen cores to scale to address a broad swath of market segments. The Summit Ridge processors on display featured 8 cores and 16 threads.

[...] Zen uses the same 14nm GlobalFoundries FinFET process that it employs on its Polaris GPUs. The process provides a nice improvement over the 28nm process used with the Excavator and Steamroller microarchitectures. Zen CPUs will drop into the AM4 chipset that debuted with the Bristol and Stony Ridge products. The AM4 chipset supports DDR4, PCIe 3.0, Next-Gen I/O, USB 3.1 Gen 2, NVMe and SATA Express. AMD added SMT (Simultaneous Multi-Threading), a new cache hierarchy and increased branch prediction capabilities to the Zen core to attain its ambitious IPC goals.

The company added a micro-op cache, which helps with better instruction predictions, to increase ILP (Instruction Level Parallelism). AMD also added a wider execution width and improved instruction scheduling to boost ILP (and thus IPC). The company claims the optimizations provide 75 percent more scheduling capacity and a 50 percent increase in instruction width over its previous-generation processors.

Zen will be available "in volume" in 2017. Also on display was a 32 core/64 thread "Naples" server CPU.

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