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There's plenty of room at the bottom:
For more than a decade, engineers have been eyeing the finish line in the race to shrink the size of components in integrated circuits. They knew that the laws of physics had set a 5-nanometer threshold on the size of transistor gates among conventional semiconductors, about one-quarter the size of high-end 20-nanometer-gate transistors now on the market. Some laws are made to be broken, or at least challenged.
A research team led by faculty scientist Ali Javey at the Department of Energy's Lawrence Berkeley National Laboratory (Berkeley Lab) has done just that by creating a transistor with a working 1-nanometer gate. For comparison, a strand of human hair is about 50,000 nanometers thick. "We made the smallest transistor reported to date," said Javey, lead principal investigator of the Electronic Materials program in Berkeley Lab's Materials Science Division. "The gate length is considered a defining dimension of the transistor. We demonstrated a 1-nanometer-gate transistor, showing that with the choice of proper materials, there is a lot more room to shrink our electronics."
[...] "This work demonstrated the shortest transistor ever," said Javey, who is also a UC Berkeley professor of electrical engineering and computer sciences. "However, it's a proof of concept. We have not yet packed these transistors onto a chip, and we haven't done this billions of times over. We also have not developed self-aligned fabrication schemes for reducing parasitic resistances in the device. But this work is important to show that we are no longer limited to a 5-nanometer gate for our transistors. Moore's Law can continue a while longer by proper engineering of the semiconductor material and device architecture."
MoS2 transistors with 1-nanometer gate lengths (DOI: 10.1126/science.aah4698) (DX)
(Score: 1) by Z-A,z-a,01234 on Monday October 10 2016, @11:25AM
"... chips are still more or less doubling in density from node to node, says Andrew Kahng, a professor at the University of California, San Diego, and an expert on high-performance chip design. But for Kahng, the steady progression of node names masks deeper problems. There is a difference, he says, between “available density” (how closely you can pack circuits and wires on a chip) and “realizable density” (what you can actually put into a competitive commercial product)."
http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated [ieee.org]
(Score: -1, Offtopic) by Anonymous Coward on Monday October 10 2016, @11:31AM
Tell that to my wife.
(Score: -1, Troll) by Anonymous Coward on Monday October 10 2016, @04:39PM
I did. We had a sensible chuckle together, then fucked.