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Rice researchers change graphene to help channel heat away from electronics.
A few nanoscale adjustments may be all that is required to make graphene-nanotube junctions excel at transferring heat, according to Rice University scientists.
The Rice lab of theoretical physicist Boris Yakobson found that putting a cone-like "chimney" between the graphene and nanotube all but eliminates a barrier that blocks heat from escaping.
Heat is transferred through phonons, quasiparticle waves that also transmit sound. The Rice theory offers a strategy to channel damaging heat away from next-generation nano-electronics.
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Anyone can make an omelet with eggs. The trick is to make one with none.
(Score: 2, Interesting) by Anonymous Coward on Monday January 16 2017, @07:29PM
Stacking layers of complex processor cores on one chip seems unlikely in the near future. At the start of this article https://en.wikipedia.org/wiki/Semiconductor_device_fabrication#List_of_steps [wikipedia.org] it mentions that there are often 300 processing steps in current wafer production. The link goes to a list of the steps that are commonly used, but these are mixed and matched depending on the types of devices being built. Even a small error rate (process variation, etc) in each of these steps reduces the overall yield of good devices from a 300mm wafer.
A good friend is an industry veteran and he says that every new generation starts out with low or zero yield. After intense development, simpler products can be raised to near 100% yield.
Adding another whole layer of processors on top would (approx.) double the number of processing steps, doubling the processing time from current 6-8 weeks for each wafer and greatly reducing yield unless every step was even closer to perfect.
(Score: 2) by takyon on Tuesday January 17 2017, @01:19AM
We already have a type of stacked/layered device: 3D/vertical NAND flash.
When yields aren't good enough, you could still sell a product by disabling faulty cores. A 3D chip with more cores has more die area that could be disabled.
There are alternate means of constructing the chip, such as molecular self-assembly, that might allow faster production compared to lithography (and more suited to the stacking). At the very least, there's active research from all angles, and a realization that EUV lithography has serious problems and delays associated with it.
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