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from the Good,-Fast,-and...-what-IS-the-price? dept.
Details about an upcoming Intel 3D XPoint SSD for datacenters have leaked:
Multiple leaks in Chinese-language media apparently outline the performance specifications of Intel's forthcoming Optane P4800X Series Cold Stream PCIe Add-In-Card, which is the company's first 3D XPoint-powered SSD. If Intel follows its trend of releasing enthusiast variants of its enterprise SSDs, we could see the NVMe DC P4800X head to the desktop soon. We treat any leak with suspicion, but in this case we also found a declaration of conformity certificate on Intel's site. The document confirms the name of the device and that it uses 3D XPoint, thus lending some credibility to the leak. We also found a reference to an unreleased DC P4500 Cliffdale SSD series.
[...] The enterprise isn't as sensitive to high prices if the value proposition is compelling enough, and as such, Intel's 375GB Cold Stream Optane DC P4800X is destined for the data center. The SSD features the standard PCIe 3.0 x4 connection and offers up to 2,400/2,000 MB/s of sequential read/write throughput over the NVMe interface. Cold Stream also blows in with up to 550,000/500,000 random read/write IOPS. The performance figures, while impressive, do not entirely encompass the benefits of using 3D XPoint. The new speedy media offers amazing performance at low queue depths and unwavering mixed workload performance, which are the most important metrics for actual applications. We cover some of the finer points of the 3D XPoint performance profile in our 3D XPoint Guide.
The DC P4800X purportedly offers up to 30 DWPD (Drive Writes Per Day) of endurance, which measures how many times you can fill the drive per day over the warranty period. 30 DWPD is unheard of for NAND-based SSDs; the most endurant modern SSDs top out at 10 DWPD. The DWPD metric can be muddy due to differing capacities, but overall, the DC P4800X can absorb up to 12.3PB of data during its service life. Intel's 450GB DC P3520 SSD, which is NAND-based, can withstand only 590TB, so apparently, 3D XPoint offers almost 21x more endurance than NAND.
(Score: 2) by TheRaven on Saturday February 11 2017, @04:43PM
sudo mod me up
(Score: 0) by Anonymous Coward on Saturday February 11 2017, @09:51PM
Fragmentation is not 'free'. With better memory techs it is cheaper. You still have to put the stuff back together. Also linear read in memory is always faster than fragmented read. Why? Because of burst DMA and caches. Now is it as noticeable as say on a spinny drive? No. But the cost is there. Always.
For example I hear people say ext4 fragmentation is not an issue. I can prove that to be false. Fragment a file say 10 gig and 5000 extents. Now copy that file to another drive. It will take considerably longer than a linear copy. Delete is the same thing. To blow the file away takes a decent amount of time. Whereas an unfragmented file deletes nearly instantly.
I see xpoint as another tier in memory currently. It is too narrow for which company makes it and too expensive to replace nand flash. I could however see companies putting a block of this in front of nand as a cache. So you get good solid linear read/write and the benefits of random r/w from the xpoint. Eventually if others start making it then we can talk about price/size competition. Even just replacing the accounting/recovery data from nand to xpoint could be an interesting win. I see it as at first replacing dram as cache and in microcontroler/storage areas. It is almost designed for it.
(Score: 2) by TheRaven on Monday February 13 2017, @11:45AM
You still have to put the stuff back together. Also linear read in memory is always faster than fragmented read. Why? Because of burst DMA and caches.
DMA can do scatter-gather on any vaguely modern system, so there's a tiny overhead from a more complex program sent to the DMA controller, but it's unlikely to be measurable. Caches typically have 64-byte lines, so you're going to be scattering the data all over caches. Intel DMA controllers are cache coherent with the L3 cache, but are not permitted to allocate more than 2 ways in an 8-way set-associative cache to avoid starving the CPU. The caches are virtually indexed, physically tagged, and so a linear (in virtual memory) write from the DMA is going to distribute the writes evenly all over a quarter of the cache, whereas a non-contiguous access will clump in places, but that only matters for the data in the buffer cache (where it's already fragmented) and is completely irrelevant to the storage side of the DMA interface.
sudo mod me up