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posted by CoolHand on Tuesday July 11 2017, @05:49PM   Printer-friendly
from the embrace-extend-extinguish dept.

Here's a statement that would have been unimaginable in previous years: Ubuntu has arrived in the Windows Store. As promised back in May, you can now download a flavor of the popular Linux distribution to run inside Windows 10. It won't compare to a conventional Ubuntu installation, as it's sandboxed (it has limited interaction with Windows) and is focused on running command line utilities like bash or SSH. However, it also makes running a form of Linux relatively trivial. You don't have to dual boot, install a virtual machine or otherwise jump through any hoops beyond a download and ticking a checkbox.

Source: Engadget


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  • (Score: 2) by kaszz on Tuesday July 11 2017, @10:38PM (4 children)

    by kaszz (4211) on Tuesday July 11 2017, @10:38PM (#537829) Journal

    Memory handling and compiler optimizations seems likely as you say.

    On the hardware side for synthesize, place and route FPGA. It seems a fast memory bus and definitely a large processor cache (Lx) speeds up completion of the task. Is that your experience too? additional tips?
    Additional cores should be a good thing but utilization of those seems dismal for this kind of application.

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  • (Score: 2) by bob_super on Tuesday July 11 2017, @11:07PM (3 children)

    by bob_super (1357) on Tuesday July 11 2017, @11:07PM (#537835)

    (definitely offtopic)
    Lots of bandwidth, lots of cache, and high clock speeds are definitely more important than going beyond 8 cores. The Xilinx tools only use 8 cores briefly, and spend a lot of time between 1 and 4 (that's slowly getting better). So single thread optimum throughput, with enough memory architecture to cycle through an 8 to 32 GB chunk of RAM used for the database...

    The new i9-7820 seems like the best bang for the buck, until we get specs and benchmarks for Ryzen 9. At the cost of the waiting engineer, the i9 is still likely to win even if it's 50% more expensive.
    I wouldn't look at server parts: the slower cores are not our friend, and I have never noticed a need for ECC (YMMV). I just wish my PHB would get that.

    • (Score: 2) by kaszz on Tuesday July 11 2017, @11:54PM (2 children)

      by kaszz (4211) on Tuesday July 11 2017, @11:54PM (#537851) Journal

      Is the Xilinx tool spending so much time in a single core that having 2 or 4 is in the area of diminishing returns? From your experiences it seems 2 cores is almost an optimal point. A finer optimization is if it's more important with local processor cache vs fast memory bus, if one has to choose one over the other.

      • (Score: 2) by bob_super on Wednesday July 12 2017, @12:16AM (1 child)

        by bob_super (1357) on Wednesday July 12 2017, @12:16AM (#537866)

        In the last 3 years, they moved a lot of the single-threaded stuff to 2 and 4 threads (Syn, Route), so not having at least 4 cores is a costly savings.
        Having at least HT to accommodate the parts where they can spawn 8 threads will save time (reports). But if a company is paying engineers, there is no reason to skimp on $900 for a 8/16 chip+mobo (1500ish for a headless machine) to give each thread its own core. I suspect future Vivado versions will keep trying to add more threads as chips get bigger but clocks don't get faster.

        • (Score: 2) by kaszz on Wednesday July 12 2017, @02:29AM

          by kaszz (4211) on Wednesday July 12 2017, @02:29AM (#537916) Journal

          So even they can make progress ;) Is the UI still crap and crashy? such that makefiles makes the day?
          Is there some kind of powerful shared server pool for doing the synthesis or is everyone doing that on their own workstation?

          Any preferences on DRAM types or is it just the more Gbit/s the better? I noticed that anything above DDR2 have significant latency times for random access when looking at the communication setup.

          What's a Vivado version?