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http://www.tomshardware.com/news/pcie-4.0-5.0-pci-sig-specfication,35325.html
PCIe is the ubiquitous engine that pulls a big part of the computing locomotive down the track—it touches nearly every device in your computer. As such, it is the linchpin for the development of many other technologies, such as storage, networking, GPUs, chipsets, and many other devices. Considering its importance, it isn't surprising to find the PCI-SIG with 750 members worldwide. Unfortunately, large organizations tend to move slowly, and PCIe 4.0 is undoubtedly late to market. PCIe 3.0 debuted in 2010 within the normal four-year cadence, but PCIe 4.0 isn't projected to land in significant quantities until the end of 2017—a seven-year gap.
PCI-SIG representatives attributed part of the delay to industry stagnation. The PCIe 3.0 interface was sufficient for storage, networking, graphics cards, and other devices, for the first several years after its introduction. Over the last two years, a sudden wellspring of innovation exposed PCIe 3.0's throughput deficiencies. Artificial intelligence craves increased GPU throughput, storage devices are migrating to the PCIe bus with the NVMe protocol, and as a result, networking suddenly has an insatiable appetite for more bandwidth.
The industry needs PCIe 4.0 to land soon, and PCI-SIG assures us it will ratify the new specification by the end of 2017. The sluggish ratification process hasn't hampered adoption entirely, though. Several IP vendors already offer 16GT/s controllers, and many vendors have already implemented PCIe 4.0 PHYs into their next-generation products. These companies are plowing ahead with the 0.9 revision of the specification, whereas the final ratified spec debuts at 1.0. PCI-SIG says it is accelerating the development and feedback processes, along with simplifying early specification revisions, in a bid to reduce time to market for future specifications. PCI-SIG indicates that PCIe 4.0 will be a short-lived specification because the organization has fast-tracked PCIe 5.0 for final release in 2019.
[...] AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
(Score: 4, Insightful) by forkazoo on Friday September 01 2017, @01:12AM (1 child)
If they tried to roll out 32 GT per lane today, it'd be impractical and terribly expensive. That's why they are targeting that speed for the 2020 spec. They aren't stopping at 16, they are just rolling it out as a huge advance on the current state of the art and then going from there once that's out. It's not particularly unreasonable for a 25 Gb NIC to use 2 PCIe lanes in the mean time.
Faster is better, all other things being equal, but there are a lot of hard problems, and nothing comes for free. (And hell, I am still waiting for 10 Gb to become ubiquitous, let alone 25!)
(Score: 2) by bob_super on Friday September 01 2017, @01:57AM
With 25G becoming more commonplace in data centers, it does matter a lot that you need 2 PCIe lanes. Because 100G connection is 8 lanes, and a 400G connection is a whopping 64 lanes.
40G is still 3 lanes, when it would be 2 at 25G.
Those have a cost, especially when Intel plays PCIe availability games.
Proper 25GT/s PCB design has a cost, too. But not as high as the processor PCIe tax.