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posted by martyb on Thursday October 05 2017, @12:12PM   Printer-friendly
from the please-let-the-vapors-condense dept.

From the lowRISC project's blog:

A high quality, upstream RISC-V backend for LLVM is perhaps the most frequently requested missing piece of the RISC-V software ecosystem… As always, you can track status here and find the code here.

RV32

100% of the GCC torture suite passes for RV32I at -O0, -O1, -O2, -O3, and -Os (after masking gcc-only tests). MC-layer (assembler) support for RV32IMAFD has now been implemented, as well as code generation for RV32IM.

RV64

This is the biggest change versus my last update. LLVM recently gained support for parameterising backends by register size, which allows code duplication to be massively reduced for architectures like RISC-V. As planned, I've gone ahead and implemented RV64I MC-layer and code generation support making use of this feature. I'm happy to report that 100% of the GCC torture suite passes for RV64I at O1, O2, O3 and Os (and there's a single compilation failure at O0). I'm very grateful for Krzysztof Parzyszek's (QUIC) work on variable-sized register classes, which has made it possible to parameterise the backend on XLEN in this way. That LLVM feature was actually motivated by requirements of the Hexagon architecture - I think this is a great example of how we can all benefit by contributing upstream to projects, even across different ISAs.

[...] Community members Luís Marques and David Craven have been experimenting with D and Rust support respectively.

[...] Approach and philosophy

As enthusiastic supporters of RISC-V, I think we all want to see a huge range of RISC-V core implementations, making different trade-offs or targeting different classes of applications. But we don't want to see that variety in the RISC-V ecosystem result in dozens of different vendor-specific compiler toolchains and a fractured software ecosystem. Unfortunately most work on LLVM for RISC-V has been invested in private/proprietary code bases or short-term prototypes. The work described in this post has been performed out in the open from the start, with a strong focus on code quality, testing, and on moving development upstream as quickly as possible - i.e. a solution for the long term.


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  • (Score: 2) by Azuma Hazuki on Thursday October 05 2017, @07:22PM

    by Azuma Hazuki (5086) on Thursday October 05 2017, @07:22PM (#577585) Journal

    I was just about to ask what the use of a 128-bit ISA would be, and then saw this. Thanks :) That is absolutely brilliant, as it means a single IPv6 address can fit in, if I understand this right, one register of said CPU.

    --
    I am "that girl" your mother warned you about...
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