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HPC Chips Abound

posted by Fnord666 on Sunday October 15 2017, @07:07PM   
from the watch-for-bugs-at-the-chip-buffet dept.

takyon writes:

High Performance Computing (HPC) Chips – A Veritable Smorgasbord?

No this isn't about the song from Charlotte's Web or the Scandinavian predilection for open sandwiches; it's about the apparent newfound choice in the HPC CPU market.

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'.

In fact, it's not just in the x86 market where there is now a genuine choice. Soon we will have at least two credible ARM v8 ISA CPUs (from Cavium and Qualcomm respectively) and IBM have gone all in on the Power architecture (having at one point in the last ten years had four competing HPC CPU lines – x86, Blue Gene, Power and Cell).

In fact, it may even be Intel that is left wondering which horse to back in the HPC CPU race with both Xeon lines looking insufficiently differentiated going forward. A symptom of this dilemma is the recent restructuring of the Xeon line along with associated pricing and feature segmentation.

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Original Submission

• Re:Discussion and Comparison says... (Score: 3, Informative) by RamiK on Sunday October 15 2017, @10:34PM

  by RamiK (1813) on Sunday October 15 2017, @10:34PM (#582787)

  RISC-V will end up like MIPS, rather than like ARM, due to too much flexibility allowed in the per-chip ABIs.

  No. RISC-V standardized the extension mechanism to prevent the per-chip ABIs fragmentation that crippled MIPS (off the v2 draft ISA manual):

  Standard-Compatible Global Encodings
  A complete or global encoding of an ISA for an actual RISC-V implementation must allocate a unique non-conflicting prefix for every included instruction encoding space. The bases and every standard extension have each had a standard prefix allocated to ensure they can all coexist in a global encoding.
  A standard-compatible global encoding is one where the base and every included standard extension have their standard prefixes. A standard-compatible global encoding can include non-standard extensions that do not conflict with the included standard extensions. A standard-compatible global encoding can also reallocate standard prefixes to non-standard extensions if the associated standard extensions are not included in this global encoding. In other words, a standard extension must use its standard prefix if included in a standard-compatible global encoding, but otherwise
  its prefix is free to be reallocated.

  The constraints allow a common toolchain to target the standard subset of any RISC-V standard-compatible global encoding, by specifying the supported standard extensions in tool command-line flags.

  The J-series of SuperH clone processors seems a more likely bet in my book

  Why? Once the patent is up you could see just as much fragmentation. Only, unlike RISC-V, there's no mechanism to deal with someone adding extra instructions.

  but they need to tape out a 'Pi alternative' chip in the next two years or less

  SiFive Freedom U500 can be evaluated on a $3.5k FPGA kit and should fit the RasPi3\ODROID-C2 space once produced on both cost and performance.

  There are no serious plans for making a RISC-V desktop ecosystem

  The x86 desktop market is a high-risk, low-reward venture. You're restricted to 4 instructions wide out-of-order superscalar pointer addressing designs since there's too much code to rewrite otherwise. Closest I've seen anyone coming near it was ARM's recent A75 that's targeting smartphones.

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