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posted by martyb on Thursday October 19 2017, @08:32AM   Printer-friendly
from the shrinking-a-Cray-to-fit-in-your-pocket dept.

Samsung has qualified its 8nm "low power plus" process for production 3 months earlier than planned. It is a slightly improved version of the company's 10nm process, and a stop-gap before Samsung begins production of a 7nm process using extreme ultraviolet (EUV) lithography. TSMC will release its 7nm process chips before Samsung, but won't use EUV for the initial generation. Samsung's 8LPP chips will improve power consumption by 10% and reduce die size by 10% (compared to 10LPP):

Years ago, Samsung seemed to have bet on the fact that 10nm will be a long-lasting process generation, so it prioritized it over the 7nm node. Meanwhile, TSMC decided to skip the 10nm node entirely and go straight to 7nm, with its own stop-gap at 12nm, which is essentially a slightly improved 16nm process.

TSMC seems to have gotten this one right, but Samsung could also achieve early expertise on EUV lithography, which could be the future of process technology. In other words, TSMC may have won this battle, but Samsung may ultimately win the war (or at least the next few process generation battles).

Because 7nm will arrive later than the competition, Samsung is now doing what TSMC did with its 12nm node and will offer a small update to its 10nm process, which it calls the 8LPP generation. The new 8LPP generation brings a 10% improvement in power consumption, as well as up to 10% die area reduction, which could be translated into cost savings for Samsung's customers. Samsung promises further cost-savings due to the high yield that this process generation can achieve, as it's already based on the proven 10nm process.

Also at Engadget and ZDNet.


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  • (Score: 3, Insightful) by FatPhil on Thursday October 19 2017, @10:15AM (6 children)

    by FatPhil (863) <reversethis-{if.fdsa} {ta} {tnelyos-cp}> on Thursday October 19 2017, @10:15AM (#584461) Homepage
    Best said here, so I'll just quote:
    "But node names are misleading since they no longer bear any relation to actual chip dimensions. It is taking longer for Intel to get to each node, but it continues to deliver true Moore's Law scaling while, in some cases, the foundries have rolled out nodes that deliver little to no physical shrink. The key dimensions for Intel's 14nm node (the distances between the fins, gates and smallest metal lines) are similar to those of the foundries' 10nm processes, and it is reasonable to assume that Intel's 10nm process will be comparable to competitors' 7nm technology."
    http://www.zdnet.com/article/chipmakers-announce-7nm-technology/

    Note how some have started to remove the "nm" from the number (e.g. "8LPP"), as tech journalists are beginning to call them out on their marketting tricks.
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  • (Score: 2) by bzipitidoo on Thursday October 19 2017, @02:00PM (4 children)

    by bzipitidoo (4388) on Thursday October 19 2017, @02:00PM (#584541) Journal

    All these measures-- MHz/GHz, die size, even a whole suite of benchmarks-- can be gamed. The GPU can be pretty important. I've seen a 350MHz system with a Pentium II outperform a 1GHz system with a Pentium III, because the P3 system was using Intel's horribly slow integrated graphics, borrowing RAM from its already underwhelming 256M available, while the P2 had Nvidia. Hard drive speed is another factor.

    • (Score: 2) by takyon on Thursday October 19 2017, @02:06PM (3 children)

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday October 19 2017, @02:06PM (#584546) Journal

      Not sure why hard drive speed would be relevant to comparing 2 CPUs unless they were released many years apart. HDD is a bottleneck in 2017, not the CPU.

      The important part about the new process is "improve power consumption by 10% and reduce die size by 10% (compared to 10LPP)". If you can believe that much, then you have an idea of its capabilities.

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      • (Score: 2) by FatPhil on Thursday October 19 2017, @10:24PM (2 children)

        by FatPhil (863) <reversethis-{if.fdsa} {ta} {tnelyos-cp}> on Thursday October 19 2017, @10:24PM (#584948) Homepage
        10% reduction in die size implies a 5% linear density increase (pitch, node size decrease). That's not 10->8, or any of the other numbers being flung around, in any language.
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        • (Score: 2) by takyon on Friday October 20 2017, @02:12AM (1 child)

          by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday October 20 2017, @02:12AM (#585056) Journal

          I didn't say the "-nm" nomenclature wasn't a lie. I said, "pay attention to these other numbers".

          AnandTech has been pretty good at tracking this: https://www.anandtech.com/show/11946/samsungs-8lpp-process-technology-qualified-ready-for-production [anandtech.com]

          We all know that Moore's law scaling is dying, but improvements are still a good thing. Some industries would kill to improve efficiency by 10%.

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          • (Score: 2) by FatPhil on Friday October 20 2017, @06:03AM

            by FatPhil (863) <reversethis-{if.fdsa} {ta} {tnelyos-cp}> on Friday October 20 2017, @06:03AM (#585129) Homepage
            Very nice to see so many comparisons side-by-side, thanks for the link, and now I've done some sniffing around on the wikipedia pages too, and I think I've worked out what the numbers *mean*.

            I think at a certain point in time they decided that the number shouldn't track the linear feature size any more, but preserved the current number/process equivalence while transitioning to the new bogonumbers. After that point, they decided to scale the number such that it shrank (looking like a linear measure) at the same rate that the feature size shrank (as measured in area). So if they actually shrank the size by 13%, they would decrease the marketting number by 17%. I've not extrapolated back to work out at what point this bogosity kicked in, but I'm guessing it was last decade.

            Or maybe I'm John Nash, and spotting patterns where there are none.
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  • (Score: 2) by takyon on Thursday October 19 2017, @02:02PM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday October 19 2017, @02:02PM (#584542) Journal

    It doesn't matter. You have the comparison to "10LPP".

    It would be nice to get the transistors per sq. mm. measurement like Intel is pushing for.

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