Stories
Slash Boxes
Comments

SoylentNews is people

posted by martyb on Thursday October 26 2017, @06:01AM   Printer-friendly
from the quite-a-bit-better dept.

Researchers at MIT, Intel, and ETH Zurich have improved on-package DRAM performance by 33-50% using a new cache management scheme that they call Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation (Banshee):

The researchers developed a new data management scheme relying on a hash function they developed to reduce the metadata burden. Yu and his colleagues' new system, dubbed Banshee, adds three bits of data to each entry in the table. One bit indicates whether the data at that virtual address can be found in the DRAM cache, and the other two indicate its location relative to any other data items with the same hash index.

"In the entry, you need to have the physical address, you need to have the virtual address, and you have some other data," Yu says. "That's already almost 100 bits. So three extra bits is a pretty small overhead."

There's one problem with this approach that Banshee also has to address. If one of a chip's cores pulls a data item into the DRAM cache, the other cores won't know about it. Sending messages to all of a chip's cores every time any one of them updates the cache consumes a good deal of time and bandwidth. So Banshee introduces another small circuit, called a tag buffer, where any given core can record the new location of a data item it caches.

Also at MIT.

Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation (arXiv)


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 0) by Anonymous Coward on Thursday October 26 2017, @08:11AM (1 child)

    by Anonymous Coward on Thursday October 26 2017, @08:11AM (#587740)

    They have some extra bits to make memory lookups faster.

    I hope nobody gets 'special' patents on this stuff, since it appears to be basic engineering rather than a novel new device, concept, design, or feature.

  • (Score: 2) by c0lo on Thursday October 26 2017, @10:25AM

    by c0lo (156) Subscriber Badge on Thursday October 26 2017, @10:25AM (#587748) Journal

    I hope nobody gets 'special' patents on this stuff, since it appears to be basic engineering rather than a novel new device, concept, design, or feature.

    Guess where the control for that "tag buffer" will be implemented? ...No? ... Really?...
    Here's the hint: it's a place between all those cores on the chip; that place which, if you disable the use of it [soylentnews.org], your CPU cache loses all its "memory of what is stored where".

    So... are you still worried about patents now?

    --
    https://www.youtube.com/watch?v=aoFiw2jMy-0 https://soylentnews.org/~MichaelDavidCrawford