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posted by martyb on Friday March 02 2018, @07:55AM   Printer-friendly
from the small-details dept.

Imec and Cadence Tape Out Industry's First 3nm Test Chip

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

A tape-out is the final step before the design is sent to be fabricated.

Meanwhile, Imec is looking towards nodes smaller than "3nm":

[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

Also at EE Times.

Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


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  • (Score: 2) by VLM on Friday March 02 2018, @01:48PM (5 children)

    by VLM (445) Subscriber Badge on Friday March 02 2018, @01:48PM (#646346)

    shrinking continues

    Sure about that? Its not really an engineering thing, any more than the conversion of K M G from powers of two to powers of ten was an actual improvement but was instead a marketing thing. I'm cynical enough about modern marketing to suspect that no, there isn't "shrinking continues" not at the rate you're thinking, and possibly the projected 2.5 and 1.5 processes are just going to be cherry picked marketing scams.

    Instead of theoretical artwork, show me the measured lower capacitance / higher Ft specs of the transistors... then I'll believe it. Till then, I can draw creative pictures of imaginary "moon rockets" as well as they can.

    The first derivative is still positive, however small its becoming, I'm not claiming its flatlined or negative, not yet, but that day is surely coming and its gonna hit zero sooner or later. Thats an interesting story.

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  • (Score: 0) by Anonymous Coward on Friday March 02 2018, @03:29PM (3 children)

    by Anonymous Coward on Friday March 02 2018, @03:29PM (#646416)

    Sure the day is coming... Can't have 0-atoms wide wires.
    But it has not come yet.

    Warning/Disclosure: I worked at Imec for more than 15 years as a researcher (not a marketeer, mind you), so I'll claim some knowledge of the topic.

    • (Score: 2) by takyon on Friday March 02 2018, @05:11PM (2 children)

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday March 02 2018, @05:11PM (#646482) Journal

      We can go smaller than 0.1 atoms!

      http://hplusmagazine.com/2011/11/01/femtocomputing/ [hplusmagazine.com]

      But in seriousness, there are a number of paths to better hardware "performance" (what that actually means can vary if new forms of computing are used):

      • We scale as much as possible, below even 1.5nm, down to the neighborhood of 0.5nm and individual atoms.
      • A new material could raise clock speeds. That might require a massive increase in core count to remain physically possible.
      • Switch to photonic for everything on the chip, including transistors.
      • Stacks. Stacks for days. With 3D NAND, we've proven that transistors can be stacked in a commercial product. If there's a way to stack tens of thousands of cores and have 100% of them operating at a given time, it will be found.
      • Focus on a new type of computing, such as quantum, AI/tensor/machine learning, or neuromorphic. SoCs are already starting to include an AI chip alongside CPU and GPU. It would be interesting to see all 5 come in one system. Neuromorphic is supposed to be low power so it could be stacked more easily than a traditional CPU and quickly reach brain-like density and enable "strong AI".
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      • (Score: 2) by frojack on Friday March 02 2018, @07:38PM (1 child)

        by frojack (1554) on Friday March 02 2018, @07:38PM (#646573) Journal

        Yet just a few years ago (2012) we were assured by industry experts that 22nm was reaching a dead end, and any hope of 14 was delusional thinking and of course Moore's Law was dead.
        In 2014 the impossible 14nm appeared in commercial quantities. iPhones got thinner.l
        Experts once again gave scientific sounding explanations why this was it, the end of the die shrinkage was reached.

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  • (Score: 2) by takyon on Friday March 02 2018, @04:53PM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday March 02 2018, @04:53PM (#646472) Journal

    Well, the transistors per mm2 continues to rise with new processes. It would be nice if numbers like that were provided in every press release about "Xnm", but whatever.

    Check out the first and second graphs here:

    https://seekingalpha.com/article/4151376-tsmc-intel-lead-semiconductor-processes?page=2 [seekingalpha.com]

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