Imec and Cadence Tape Out Industry's First 3nm Test Chip
The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.
A tape-out is the final step before the design is sent to be fabricated.
Meanwhile, Imec is looking towards nodes smaller than "3nm":
[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.
Also at EE Times.
Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
(Score: 0) by Anonymous Coward on Friday March 02 2018, @03:29PM (3 children)
Sure the day is coming... Can't have 0-atoms wide wires.
But it has not come yet.
Warning/Disclosure: I worked at Imec for more than 15 years as a researcher (not a marketeer, mind you), so I'll claim some knowledge of the topic.
(Score: 2) by takyon on Friday March 02 2018, @05:11PM (2 children)
We can go smaller than 0.1 atoms!
http://hplusmagazine.com/2011/11/01/femtocomputing/ [hplusmagazine.com]
But in seriousness, there are a number of paths to better hardware "performance" (what that actually means can vary if new forms of computing are used):
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by frojack on Friday March 02 2018, @07:38PM (1 child)
Yet just a few years ago (2012) we were assured by industry experts that 22nm was reaching a dead end, and any hope of 14 was delusional thinking and of course Moore's Law was dead.
In 2014 the impossible 14nm appeared in commercial quantities. iPhones got thinner.l
Experts once again gave scientific sounding explanations why this was it, the end of the die shrinkage was reached.
No, you are mistaken. I've always had this sig.
(Score: 3, Insightful) by takyon on Friday March 02 2018, @08:33PM
There was never any consensus among experts. You're attacking nobody in particular.
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