Stories
Slash Boxes
Comments

SoylentNews is people

posted by martyb on Thursday March 08 2018, @02:24PM   Printer-friendly
from the it's-just-a-small-RISC dept.

Wave Computing Adopts Low Power MIPS 64-bit Multi-Threaded Core

Wave Computing [...] announced today that it has selected a 64-bit Multi-Threaded processor core from MIPS Technologies for future AI solutions. Wave will use the MIPS core in its next generation of Dataflow Processing Unit (DPU) chips that will ship in Wave's future deep learning systems to handle device control functions including management of the real-time operating system (RTOS) and system-on-chip (SoC) subsystem.

From a MIPS press release:

As design complexity and software footprints continue to increase, the 64-bit MIPS architecture is being used in an even broader set of datacenter, connected consumer devices, networking products, and emerging AI applications. In addition to Wave, companies including Mobileye, Fungible, ThinCI, and DENSO, among others, are using the MIPS 64-bit processor core as they develop ground-breaking AI applications. [...] Last August, Denso group company NSITEXE, Inc. announced that it licensed the newest MIPS CPU to drive enhanced in-vehicle electronic processing.

Related: MIPS Strikes Back: 64-bit Warrior I6400 Arrives
PEZY's Next Many-Core Chip Will Include a MIPS 64-Bit CPU
ARM Cortex-A35, Snapdragon 820, and New Imagination MIPS Processors
Linux-Based, MIPS-Powered Russian All-in-One PC Launched
Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 0) by Anonymous Coward on Thursday March 08 2018, @07:59PM (1 child)

    by Anonymous Coward on Thursday March 08 2018, @07:59PM (#649668)

    Pointless and incorrect. There is no PAE for amd64. You're thinking of virtual and physical address spaces. Neither is truly 64-bit wide in any current implementation.

  • (Score: 0) by Anonymous Coward on Friday March 09 2018, @07:43PM

    by Anonymous Coward on Friday March 09 2018, @07:43PM (#650185)

    A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 1. With IA-32e paging, linear address are translated using a hierarchy of in-memory paging structures located using the contents of CR3. IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses. Although 52 bits corresponds to 4 PBytes, linear addresses are limited to 48 bits; at most 256 TBytes of linear-address space may be accessed at any given time.

    ( Intel® 64 and IA-32 Architectures Software Developer’s Manual [intel.com] Ch. 4.5 IA-32E PAGING )

    The tables and diagrams explain what "direct" means here.