Stories
Slash Boxes
Comments

SoylentNews is people

posted by martyb on Thursday March 08 2018, @02:24PM   Printer-friendly
from the it's-just-a-small-RISC dept.

Wave Computing Adopts Low Power MIPS 64-bit Multi-Threaded Core

Wave Computing [...] announced today that it has selected a 64-bit Multi-Threaded processor core from MIPS Technologies for future AI solutions. Wave will use the MIPS core in its next generation of Dataflow Processing Unit (DPU) chips that will ship in Wave's future deep learning systems to handle device control functions including management of the real-time operating system (RTOS) and system-on-chip (SoC) subsystem.

From a MIPS press release:

As design complexity and software footprints continue to increase, the 64-bit MIPS architecture is being used in an even broader set of datacenter, connected consumer devices, networking products, and emerging AI applications. In addition to Wave, companies including Mobileye, Fungible, ThinCI, and DENSO, among others, are using the MIPS 64-bit processor core as they develop ground-breaking AI applications. [...] Last August, Denso group company NSITEXE, Inc. announced that it licensed the newest MIPS CPU to drive enhanced in-vehicle electronic processing.

Related: MIPS Strikes Back: 64-bit Warrior I6400 Arrives
PEZY's Next Many-Core Chip Will Include a MIPS 64-Bit CPU
ARM Cortex-A35, Snapdragon 820, and New Imagination MIPS Processors
Linux-Based, MIPS-Powered Russian All-in-One PC Launched
Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 2) by TheRaven on Friday March 09 2018, @10:30AM

    by TheRaven (270) on Friday March 09 2018, @10:30AM (#649904) Journal

    We picked MIPS 8 years ago. If RISC-V had been in the state now that it was then, we'd have picked RISC-V. You have two choices with MIPS now: new MIPS (r6) or old MIPS (r2 or earlier). These are different ISAs that are not compatible. ImagTec wibbled a lot about binary translation for old MIPS code to MIPSr6, but never actually shipped a binary translator. If you go MIPSr6 (which were the cores that ImagTec was trying to sell, because those were the ones definitely still in patent) then you lose existing toolchain support.

    GCC is a clusterfuck for MIPS, because all of the vendors made their own incompatible extensions and didn't do the compiler work properly (with the exception of Cavium, which has now switched entirely to ARM) and so broke every other MIPS vendor's targets and couldn't upstream things. This means that the state in GCC is pretty bad. Modifying GCC is also just pain. MIPS in LLVM is mediocre. It now works (in part because I've upstreamed a load of fixes), but it generates pretty poor code for a few common patterns and the design of the MIPS ISA makes it difficult to improve. A lot of the ImagTec work was directed at things like MIPS16 / microMIPS, which no one actually cares about, rather than improving performance and correctness.

    The entire ecosystem is broken and dying. If you want something that works now, MIPS might be it if you squint, but you're going to be taking on most of the ecosystem maintenance costs yourself because everyone else is migrating their stuff away from MIPS as fast as humanly possible.

    Oh, and LLVM's scheduler currently generates much better code for OoO cores, so if you've got an in-order design then it's less than idea. Not sure about GCC, because it's been years since I worked with any companies that cared about it.

    --
    sudo mod me up
    Starting Score:    1  point
    Karma-Bonus Modifier   +1  

    Total Score:   2