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posted by martyb on Friday March 23 2018, @06:16PM   Printer-friendly
from the RISCy-business dept.

ACM, the Association for Computing Machinery, today named John L. Hennessy, former President of Stanford University, and David A. Patterson, retired Professor of the University of California, Berkeley, recipients of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. Hennessy and Patterson created a systematic and quantitative approach to designing faster, lower power, and reduced instruction set computer (RISC) microprocessors. Their approach led to lasting and repeatable principles that generations of architects have used for many projects in academia and industry. Today, 99% of the more than 16 billion microprocessors produced annually are RISC processors, and are found in nearly all smartphones, tablets, and the billions of embedded devices that comprise the Internet of Things (IoT).

Hennessy and Patterson codified their insights in a very influential book, Computer Architecture: A Quantitative Approach, now in its sixth edition, reaching generations of engineers and scientists who have adopted and further developed their ideas. Their work underpins our ability to model and analyze the architectures of new processors, greatly accelerating advances in microprocessor design.

Source: HPCWire


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  • (Score: 2) by bzipitidoo on Saturday March 24 2018, @12:30AM (2 children)

    by bzipitidoo (4388) on Saturday March 24 2018, @12:30AM (#657328) Journal

    On modern x86 CPUs, under the hood at the microcode level, the x86 architecture is implemented with RISC, yes. But the architecture itself is decidedly CISC, and originally, the silicon was also CISC. And the architecture has only gone deeper into the CISC way, with the addition of the MMX and SSE instructions.

    I forget which generation made the leap from CISC at the gate level to emulated CISC on top of a RISC core, maybe the Pentiums?

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  • (Score: 2) by MichaelDavidCrawford on Saturday March 24 2018, @03:01AM (1 child)

    by MichaelDavidCrawford (2339) Subscriber Badge <mdcrawford@gmail.com> on Saturday March 24 2018, @03:01AM (#657355) Homepage Journal

    -ns.

    So says Michael L. Schmit in "Pentium Processor Optimization Tools".

    It's been out of print for fifteen years or so but Amazon yields the insight that it can be had used for $2.99.

    It comes with an Assembly Code "Optimizer". What it does is generate commented source code that lets you know where such things as pipeline stalls occur.

    Schmit's company disappeared not long after his book was publish. I figured it got acquired but I've never heard of any more-recent versions of his Assembly Code Optimizer.

    --
    Yes I Have No Bananas. [gofundme.com]
    • (Score: 3, Interesting) by shortscreen on Saturday March 24 2018, @04:45AM

      by shortscreen (2252) on Saturday March 24 2018, @04:45AM (#657369) Journal

      Sometimes it does. Address calculations make good candidates for parallel execution, so something like MOV EAX,[EBX+ECX*4] might run just as fast as a plain MOV EAX,[EBX]. Old-timey assembler favorites like XLAT or LOOP are probably not optimal. Chip makers pick and choose which opcodes they will optimize (in the Athlon 64 docs they refer to "direct path" and "vector path") and it seems like sometimes the cpu is built to accomodate compilers and other times the opposite is true.