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[...] Optic communications encompass all technologies that use light and transmit through fiber optic cables, such as the internet, email, text messages, phone calls, the cloud and data centers, among others. Optic communications are super fast but in microchips they become unreliable and difficult to replicate in large quanitites.
Now, by using a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure, Levy and his team have come up with a new integrated circuit that uses flash memory technology -- the kind used in flash drives and discs-on-key -- in microchips. If successful, this technology will enable standard 8-16 gigahertz computers to run 100 times faster and will bring all optic devices closer to the holy grail of communications: the terahertz chip.
Source: Smaller and faster: The terahertz computer chip is now within reach
Non-Volatile Silicon Photonics Using Nanoscale Flash Memory Technology (DOI: 10.1002/lpor.201700190) (DX)
(Score: 2) by The Mighty Buzzard on Saturday March 31 2018, @12:10PM (6 children)
I'm guessing that means it won't be ready for another thirty years or so then. That's 3-4x what current "standard" speeds are and we're not even remotely in danger of seeing a 2x clock speed increase within the next decade if the past decade is anything to go by.
My rights don't end where your fear begins.
(Score: 0) by Anonymous Coward on Saturday March 31 2018, @12:31PM (5 children)
>> That's 3-4x what current "standard" speeds are
I heard IPC was more important anyway.
(Score: 2) by The Mighty Buzzard on Saturday March 31 2018, @05:54PM (4 children)
Depends on the application, of course. A single threaded or poorly designed multi-threaded application won't see much if any benefit from improved IPC. There are a whole lot more of those combined categories than there are of well-designed multi-threaded applications.
My rights don't end where your fear begins.
(Score: 1, Informative) by Anonymous Coward on Saturday March 31 2018, @06:39PM (3 children)
By IPC do you mean instructions per clock, or inter-process communication. In this context it usually means instructions per clock, and that will benefit all but IO (including memory latency) bound applications.
https://en.wikipedia.org/wiki/Instructions_per_cycle [wikipedia.org]
(The exact same confusion had me wondering what was going on for years...)
(Score: 2) by The Mighty Buzzard on Saturday March 31 2018, @08:52PM
The latter. I hadn't enough caffeine in me yet apparently.
My rights don't end where your fear begins.
(Score: 0) by Anonymous Coward on Sunday April 01 2018, @01:46AM (1 child)
> In this context it usually means instructions per clock, and that will benefit all but IO (including memory latency) bound applications.
Up to a point, as branch prediction misses will murder performance, so your program will appear to randomly slow down to a fraction of "regular" execution speed. A user-facing program that randomly slows down to, say, 1%, is way worse than a program that's that slow all the time. Of course, you could improve the situation by speculatively executing both branches, but you have to be careful of the ever-looming spectre of a meltdown...
(Score: 2) by takyon on Sunday April 01 2018, @01:57AM
And branch prediction led to all those fun security vulnerabilities.
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