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The Taiwan Semiconductor Manufacturing Company (TSMC) has revealed a manufacturing technique (called wafer-on-wafer or WoW) that could allow CPUs and GPUs to take their first step towards vertical scaling:
Instead of one wafer per chip, future GPUs may include two or more wafers stacked vertically, which would double the performance without the need to develop new horizontal designs every 2 years. A dual wafer setup, for example, would be achieved by flipping the upper wafer over the lower one, binding both via a flip-chip package. Thus, future GPUs could include multiple wafers in one die and the operating system could detect it as a multi-processor graphics card, eliminating the need for SLI setups.
One shortcoming for this technology would be its lower manufacturing yields for sizes lower than 16 nm. If one of the stacked wafers does not pass the QA, the entire stack is discarded, leading to low yields and poor cost effectiveness. TSMC is currently working to improve this technology so that sub-12 nm processes could equally benefit from it.
Not discussed is how to deal with the heat generated in such a stack.
See also: Here's why Intel and AMD's 7nm CPU revolution is so important to the future of PCs
(Score: 2) by ese002 on Tuesday May 15 2018, @05:33PM
3D NAND is a monolith process. They don't fabricate 64 wafers and then stack them. They deposit 64 layers onto a single substrate (a relatively cheap operation) and then do a single exposure and etch through all 64 layers. It is really cool tech but only applicable to rigidly structured memory designs.