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ARM Announces the Cortex-A76

posted by martyb on Friday June 01 2018, @05:41AM   
from the how-much-does-it-cost? dept.

takyon writes:

ARM has announced its latest CPU, promising "laptop-class" performance:

So what is the Cortex A76? In Arm's words, it's a "laptop-class" performance processor with mobile efficiency. The vision of the A76 as a laptop-class processor had been emphasised throughout the TechDay presentation so it seems Arm is really taking advantage of the large performance boost of the IP to cater to new market segments such as the emerging "Always connected PCs" which Qualcomm is spearheading with their SoC platforms.

[...] In broad metrics, what we're promised in actual products using the A76 is the follows: a 35% performance increase alongside 40% improved power efficiency. We'll also see a 4x improvements in machine learning workloads thanks to new optimisations in the ASIMD pipelines and how dot products are handled. These figures are baselined on A75 configurations running at 2.8GHz on 10nm processes while the A76 is projected by Arm to come in at 3GHz on 7nm TSMC based products.

The new CPU is naturally still compatible with DynamIQ's common cluster topology and Arm envisions designs to be paired with Cortex A55s as the little more power efficient CPUs. The configuration scalability of the DynamIQ IP again was reiterated and we were presented with example configurations such as 1+7 or 2+6 with either Cortex A75 or A76 CPU IP. This presentation slide was one of the rare ones where Arm referred to the area size of the A76, pointing out that the A75 still had better PPA and thus might still be a valid design choice for companies, depending on their needs. One comparison that was made during the event is that in terms of area, three A76's with larger caches would fit inside the size of a Skylake core – all while within 10% of the IPC of the Intel CPU, but obviously there's also process node scaling considerations to take into account.

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Original Submission

• How's RISC-V? How's RISC-V? (Score: 3, Interesting) by Wootery on Friday June 01 2018, @09:35AM (4 children)

  by Wootery (2341) on Friday June 01 2018, @09:35AM (#687166)

  Not to instantly go off-topic, but... eh: anyone know how RISC-V is doing these days? How about J-Core (Open Source SuperH)?

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• Re:How's RISC-V? (Score: 3, Informative) by takyon on Friday June 01 2018, @09:44AM

  by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday June 01 2018, @09:44AM (#687171) Journal

  HiFive-Unleashed Expansion Board Opens Door for RISC-V PCs [designnews.com]

  The HiFive Unleashed is the first open-source RISC-V SoC that supports Linux. It combines SiFive's Freedom U540 RISC-V processor, a 64-bit, 4+1 multicore processor that fully supports Linux, as well as other operating systems, such as FreeBSD and Unix. The board features 8GB of DDR4 with ECC, a gigabit ethernet port, 32 MB of quad SPI flash memory, a MicroSD card slot, and an FPGA mezzanine card (FMC) connector, courtesy of Microsemi's PolarFire FPGAs, for allowing peripherals and other expansion devices to be attached to the board. Microsemi's new HiFive Unleashed Expansion Board adds several more features, including a PCIe root complex, a SATA port, M.2 SSD port, two USB ports, an HDMI connector, DDR4 memory expansion, an embedded multi-media controller (eMMC), managed NAND Flash, and a secure digital card slot.

  [...] At $1,999 and $999, respectively ($2,998 for a bundle), the Expansion Board and the HiFive Unleashed both come at price tags that won't see them competing with a less than $100 Raspberry Pi or Arduino any time soon. But it does open up an interesting discussion around RISC-V's potential for consumer computing applications—particularly if price points come down. Spending a few grand on a custom PC is not unheard of in DIY and hobbyist circles.

  RISC-V: Are we there yet…? [ultrasoc.com]

  SiFive Releases 'Expansion Board' to Build Interest in RISC-V Processor [datacenterknowledge.com]

  A look back at the RISC-V workshop in Barcelona and the RISC-V ecosystem’s growth [embedded-computing.com]

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  [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]

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• Re:How's RISC-V? Re:How's RISC-V? (Score: 2, Funny) by Anonymous Coward on Friday June 01 2018, @12:08PM (1 child)

  by Anonymous Coward on Friday June 01 2018, @12:08PM (#687198)

  Not to instantly go off-topic,

  Sorry, aristarchus beat you to it.

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  • Re:How's RISC-V? (Score: 3, Informative) by Wootery on Friday June 01 2018, @01:28PM

    by Wootery (2341) on Friday June 01 2018, @01:28PM (#687224)

    No shame in being beaten by the best.

    Parent

• Re:How's RISC-V? (Score: 0) by Anonymous Coward on Friday June 01 2018, @05:20PM

  by Anonymous Coward on Friday June 01 2018, @05:20PM (#687330)

  no, we should go instantly off topic to risc, etc. screw this arm slaveware.

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