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posted by chromas on Monday July 23 2018, @10:22PM   Printer-friendly
from the drm dept.

Hugo Landau has written a blog post about why Intel will never let hardware owners control the Management Engine. The Intel Managment Engine (ME) is a secondary microprocessor ensconced in recent Intel x86 chips, running an Intel-signed, proprietary, binary blob which provides remote access over the network as well as direct access to memory and peripherals. Because of the code signing restrictions enforced by the hardware, it cannot be modified or replaced by the user.

Intel/AMD will never allow machine owners to control the code executing on the ME/PSP because they have decided to build a business on preventing you from doing so. In particular, it's likely that they're actually contractually obligated not to let you control these processors.

The reason is that Intel literally decided to collude with Hollywood to integrate DRM into their CPUs; they conspired with media companies to lock you out of certain parts of your machine. After all, this is the company that created HDCP.

This DRM functionality is implemented on the ME/PSP. Its ability to implement DRM depends on you not having control over it, and not having control over the code that runs on it. Allowing you to control the code running on the ME would directly compromise an initiative which Intel has been advancing for over a decade.


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  • (Score: 0) by Anonymous Coward on Tuesday July 24 2018, @01:38PM

    by Anonymous Coward on Tuesday July 24 2018, @01:38PM (#711709)

    Does the RISC-V https://en.wikipedia.org/wiki/RISC-V [wikipedia.org] [wikipedia.org] CPU have an ME?

    Since RISC-V is not a CPU, but an instruction set architecture, this question is about as meaningful as the question whether the x86 instruction set architecture has a management engine. Which is, not meaningful at all.

    A processor implementing RISC-V may or may not have an equivalent to Intel's ME. That is up to whoever implements the processor. Indeed, a processor (RISC-V or otherwise) could even have a RISC-V based ME!