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Leaked benchmarks show Intel is dropping hyperthreading from i7 chips
Benchmarks found in the SiSoft Sandra database list a Core i7-9700K processor. This increases the core count from the current six cores in the 8th generation Coffee Lake parts to eight cores, but, even though it's an i7 chip, it doesn't appear to have hyperthreading available. Its base clock speed is 3.6GHz, peak turbo is 4.9GHz, and it has 12MB cache. The price is expected to be around the same $350 level as the current top-end i7s.
For the chip that will sit above the i7-9700K in the product lineup, Intel is extending the use of its i9 branding, initially reserved for the X-series High-End Desktop Platform. The i9-9900K will be an eight-core, 16-thread processor. This bumps the cache up to 16MB and the peak turbo up to 5GHz—and the price up to an expected $450.
Below the i7s will be i5s with six cores and six threads and below them, i3s with four cores and four threads.
Meanwhile, AMD's 7nm Ryzen 2 is rumored to boost instructions per clock (IPC) by 10-15% and increase the number of cores per core complex (CCX) from 4 to 8, potentially resulting in mainstream 16 core, 32 thread CPUs.
(Score: 4, Insightful) by Rich on Thursday July 26 2018, @09:24AM
I guess HT was introduced once they saw how much of their valuable silicon sat idle on average on the P4, which had a very long pipeline and wasn't too good at predicting avoidable stalls. Take a CPU with a shorter pipeline and as the predictors get better, the amount of unused logic drops. There must be a point where the gains from using the stall gaps with HT become smaller than the losses from the extra overhead for the HT logic with its second register set.
Neglecting bottleneck effects, the ballpark rule for an upper bound of gains would be: halving the fundamental blocks in stalled state means half the processing power for HT. The stalled state percentage could be estimated by theoretical upper bound of IPC (clock * execution units) and actual benchmark IPC throughput.