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posted by Fnord666 on Saturday August 11 2018, @12:53AM   Printer-friendly
from the another-day-another-CPU dept.

Although a wide range of potential applications exists for the ARMV8-M processors, developers working on secure real-time applications will certainly see the largest benefit. So far, the ARMV8-M architecture can be found in M23 and M33 Cortex-M and M35P processors. Let’s take a look at the new features included in ARMV8-M and how these processors differ from previous generation ARMV7-M parts.

[...] The ARMV8-M feature that really sets the M23, M33, and M35P apart is their support for ARM TrustZone. TrustZone is a security extension that provides hardware isolation within the microcontroller so that developers can create secure and unsecure regions. These regions can be locations in RAM, Flash, or even interrupts and peripherals. The separation between secure and unsecure regions creates isolation within the microcontroller, allowing developers to protect mission-critical code and data.

The isolation creates two new modes that the processor can be running in: secure and unsecure. When in secure mode, the executing code can access all memory within both the secure and unsecure zones. However, if the processor is executing in the unsecure zone, only the unsecure regions can be seen. The secure regions are hidden and cannot be executed from the unsecure state without special code being added, which creates a gateway to access a secure call. This makes it possible to use secure functions while hiding what is happening behind the scenes. 

There are several other new features that developers will find interesting besides the TrustZone extension. These include:

  • Simpler MPU setup
  • Flexible breakpoint configuration
  • Improved trace support
  • Instruction set enhancements
  • Dynamic reprioritization of interrupts

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  • (Score: 2) by MichaelDavidCrawford on Saturday August 11 2018, @04:49AM (2 children)

    by MichaelDavidCrawford (2339) Subscriber Badge <mdcrawford@gmail.com> on Saturday August 11 2018, @04:49AM (#720222) Homepage Journal

    ... that allocating memory from an interrupt handler is ill-advised.

    A dataflow diagram would have clued me into that instantly. Sucks to be me, I had not used them in years by then.

    --
    Yes I Have No Bananas. [gofundme.com]
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  • (Score: 2) by RS3 on Saturday August 11 2018, @05:26AM (1 child)

    by RS3 (6367) on Saturday August 11 2018, @05:26AM (#720231)

    Oh, gosh. What CPU / system architecture?

    • (Score: 3, Interesting) by MichaelDavidCrawford on Saturday August 11 2018, @07:37AM

      by MichaelDavidCrawford (2339) Subscriber Badge <mdcrawford@gmail.com> on Saturday August 11 2018, @07:37AM (#720246) Homepage Journal

      DSP/BIOS is now called TI RTOS Kernel. I liked it.

      I ported the Apple Firewire Reference Platform to DSP/BIOS. It originally targeted VxWorks. I wrote a driver for a !@#$%^&*() Firewire Link-Layer chip.

      My particular code wasn't doing any signal processing or real-time. It was to enable firewire storage for the Zaxcom Deva 3 wireless audio recorder. It sold like hotcakes.

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      Yes I Have No Bananas. [gofundme.com]