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Samsung Foundry Updates: 8LPU Added, EUVL on Track for HVM in 2019
Samsung recently hosted its Samsung Foundry Forum 2018 in Japan, where it made several significant foundry announcements. Besides reiterating plans to start high-volume manufacturing (HVM) using extreme ultraviolet lithography (EUVL) tools in the coming quarters, along with reaffirming plans to use gate all around FETs (GAAFETs) with its 3 nm node, the company also added its brand-new 8LPU process technology to its roadmap. Samsung Foundry's general roadmap was announced earlier this year, so at SFF in Japan the contract maker of semiconductors reiterated some of its plans, made certain corrections, and provided some additional details about its future plans.
First up, Samsung added another fabrication technology into its family of manufacturing processes based on its 10 nm node. The new tech is called 8LPU (low power ultimate) and, according to Samsung's usual classification, this is a process for SoCs that require both high clocks and high transistor density. Samsung's 8LPP technology, which qualified for production last year, is a development of Samsung's 10 nm node that uses narrower metal pitches to deliver a 10% area reduction (at the same complexity) as well as a 10% lower power consumption (at the same frequency and complexity) compared to 10LPP process. 8LPU is a further evolution of the technology platform that likely increases transistor density and frequency potential vs 8LPP. Meanwhile Samsung does not disclose how it managed to improve 8LPU vs. 8LPP and whether it involved advances of design rules, usage of a new library, or a shrink of metal pitches. Samsung's 8LPP and 8LPU technologies are aimed at customers who need higher performance or lower power and/or higher transistor density than what Samsung's 10LPP, 10LPC, and 10LPU processes can offer, but who cannot gain access to Samsung's 7LPP or more advanced manufacturing technologies that use EUVL. Risk production using 8LPU was set to start in 2018, so expect high-volume manufacturing to commence next year at Samsung's Fab S1 in Giheung, South Korea.
[...] By the time the new production line in Hwaseong becomes operational, Samsung Foundry promises to start risk production using its 5/4 nm node. As reported earlier this year, Samsung is prepping 5LPE, 4LPE, and 4LPP fabrication technologies, but eventually this list will likely expand. Based on what Samsung has disclosed about all three manufacturing processes so far, they will have certain similarities, which will simplify migration from 5LPE all the way to 4LPP, though the company does not elaborate. [...] One of the unexpected things that Samsung Foundry announced was start of risk production using its 3 nm node already in 2020, which is at least a year ahead of what was expected earlier. Samsung's 3 nm will be the first node to use the company's own GAAFET implementation called MBCFET (multi-bridge-channel FETs) and will officially include at least two process technologies: 3GAAE and 3GAAP (3nm gate-all-around early/plus).
Previously: Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes
Samsung Plans to Make "5nm" Chips Starting in 2019-2020
Related: GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack
(Score: 2) by takyon on Tuesday September 11 2018, @09:54AM (2 children)
Filling in beyond what fakefuck said...
Feature sizes aren't accurately described by the number they brand the process with. "14nm", "7nm", "3nm", etc. are marketing lies, although parts are getting somewhat smaller, faster, and more power efficient. There is talk about nodes smaller than "3nm" [semiengineering.com], and "0.5nm" is probably as low as they can claim without being laughed out of the building. After that, we probably have to move towards stacked layers of transistors, which requires solving heat dissipation issues. Or something much more hypothetical like femtotechnology [hplusmagazine.com]. More likely, more effort will be focused on neuromorphic and quantum computers, which won't work the same as a classical computer but could deliver great results in some areas.
HDD to SSD transition is a great speedup, but has nothing to do with Moore's law.
A lot of chips can get up to 5 GHz [wccftech.com], usually only with "turbo" features. Which is fine since a short burst of performance is what most home users need.
If AMD doubles the core count of "7nm" Zen 2 chips, desktop Ryzen could have 8 cores minimum.
DDR5 [wikipedia.org] comes first. There may not be a need for DDR6, and I would rather see something like HBM4, stacked close to the processor (hard to make that user upgradeable?).
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(Score: 1) by exaeta on Tuesday September 11 2018, @09:38PM (1 child)
Or you know, instead of making them smaller, the focus could shift to materials. So we'll get new material semiconductors every so often that can switch faster. We aren't going to make 1/2 atom wide transistors, but there's no reason we can't have a 5THz clock rate if we find something better than silicon.
The Government is a Bird
(Score: 2) by takyon on Tuesday September 11 2018, @09:56PM
Don't you run into problems with the speed of light at these clock rates?
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