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posted by martyb on Friday September 28 2018, @10:57PM   Printer-friendly
from the chip-ship-slip dept.

Intel Issues Update on 14nm Shortage, Invests $1B Into Fab Sites (Update)

Intel's CFO and interim CEO Bob Swan penned an open letter to its customers and partners today outlining the steps it is taking to address a persistent and worsening shortage of 14nm processors.

[...] The shortage impacts nearly every aspect of Intel's business, from desktops to laptops, servers and even chipsets, so Intel is making the sound business decision to prioritize high-margin products. The firm has also expanded its testing capacity by diverting some work to a facility in Vietnam.

[...] Intel's statement also assures us that processors built on its 10nm fabrication will arrive in volume in 2019. Intel had previously stated that 10nm processors would be available in 2019, but hadn't made the distinction that they would arrive in volume. That's a positive sign, as the oft-delayed 10nm production is surely a contributing factor to the shortage. Intel also cites the booming desktop PC market, which has outstripped the company's original estimates earlier this year, as a catalyst.

In either case, Intel concedes that "supply is undoubtedly tight, particularly in the entry-level of the PC market" but doesn't provide a firm timeline for when the processors will become fully available. Intel's letter also touts its $1 billion investment in 14nm fabs this year, but half of that capital expenditure was scheduled prior to its first public acknowledgement of the shortage. Given Intel's foresight into the production challenges, the prior $500 million investment was likely in response to the increases in demand and looming production shortfall.

Previously: Intel Migrates New Chipsets to "22nm" Node From "14nm"

Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed
Intel's First 8th Generation Processors Are Just Updated 7th Generation Chips
Intel Delays Mass Production Of 10 nm CPUs To 2019


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  • (Score: 2) by takyon on Saturday September 29 2018, @04:52AM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday September 29 2018, @04:52AM (#741703) Journal

    Those node names don't mean much of anything anymore, and they are defined differently by different companies.

    Intel "10nm" is said to be on part with TSMC "7nm".

    Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's [soylentnews.org]

    Why All Nodes Won’t Work [semiengineering.com]

    “We all know that the newer process geometries are more of a guide as to what the process capabilities are (transistor density and power/speed tradeoffs) than to any actual physical dimension of the process,” said Marc Greenberg, group director for product marketing, DDR, HBM, flash/storage and MIPI IP at Cadence. “The industry standard to date has been to indicate key differences in processing-for example, SiON (silicon oxynitride) versus high-k/metal gate, EUV or not-with different letter or symbol suffixes to the process. But that may eventually become new nodelets instead of new suffixes. At the 28nm node, we saw a lot of variants of the 28nm processes that were generally incompatible with each other. That created a lot of work for the IP industry to cover all of these process node variations. We also saw some of the early finFET nodes have some difficulty taking off, which was more work for the IP industry that didn’t necessarily convert into sales.”

    What is a nodelet?

    Much of the confusion around nodelets is based on marketing terminology. Numbers have blurred to the point where no one is quite sure what the numbers really signify. What TSMC and Samsung call 5nm is actually 7nm for Intel, GlobalFoundries and Imec, and the same applies for 10/7nm and 5/3nm. On top of that, there are different versions of these nodes, based on low power or high performance or cost, each of which can have its own unique twists.

    “The thought process in an established node is that if it’s in production, then you can optimize that node,” said Synopsys’ Nandra. “So you have 28nm and you know it works well and defect density is in a solid percentage. To improve that, you squeeze it a little, give it a new name like 22nm. But that doesn’t mean that it has a 22nm gate length. You’ve done something to give it better density. That shouldn’t be a big change for the IP community. But when it comes to high-speed versions, with extraction, simulation, resistances, capacitance and inductive relationship of packages, the impact of transistors as they have gone through optical shrink, all of that creates a big amount of re-working. You need a complete revalidation of the IP. Post-layout parasitic extraction can be quite a challenge. Or you need to complete a new test chip just to make sure you have not missed anything.”

    Silicon Lacks Clear Metrics [eetimes.com]

    Technology Node [wikichip.org]

    Transistor Options Beyond 3nm [semiengineering.com]

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