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posted by martyb on Wednesday November 21 2018, @07:35PM   Printer-friendly
from the What-*does*-FPGA-stand-for? dept.

As part of the company's Supercomputing 2018, a new FPGA accelerator card was announced by Xilinx. The Xilinx Alveo U280 is one of the company's pre-ACAP 16nm UltraScale+ architecture FPGA products. The U280 features 8GB of Samsung High Bandwidth Memory (HBM2) plus 32GB of DDR4 memory. The goal of the new card is to accelerate database search and analytics, machine learning inference, and other memory-bound applications.

Buried in the documentation for the card is a nugget of extremely interesting information:

"The U280 acceleration card includes CCIX support to leverage existing server interconnect infrastructure for high bandwidth, low latency cache coherent shared memory access with CCIX enabled processors including Arm and AMD." (Source: Xilinx Alveo U280 whitepaper WP50 (v1.0) accessed 16 November 2018)

We were recently at the AMD Next Horizon Event and STH friend Dr. Ian Dr. Ian Cutress at Anandtech (not a typo, that is what his SC18 badge said) touched upon this in his interview with AMD CTO Mark Papermaster. Neither in the Rome disclosure nor the interview did AMD confirm CCIX support. However, AMD publicly supports CCIX and Gen-Z and when we asked if this means Rome supports CCIX all we received was that AMD supports CCIX but has not announced a product with it yet. Arm may have chips derived from its IP with CCIX support, but AMD has a more well-defined roadmap.

https://www.servethehome.com/xilinx-alveo-u280-launched-possibly-with-amd-epyc-ccix-support/


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  • (Score: 0) by Anonymous Coward on Wednesday November 21 2018, @08:24PM (1 child)

    by Anonymous Coward on Wednesday November 21 2018, @08:24PM (#764932)

    CCIX is a high-performance, chip-to-chip interconnect architecture that provides a cache coherent framework for heterogeneous system architectures. Cache coherency is automatically maintained at all time between the central processing unit and the various other accelerators in the system. Operating over standard PCIe, CCIX supports signaling rates between 16 GT/s and 25 GT/s per link with support for port aggregation for higher performance.

    https://en.wikichip.org/wiki/ccix [wikichip.org]

  • (Score: 0) by Anonymous Coward on Thursday November 22 2018, @02:59PM

    by Anonymous Coward on Thursday November 22 2018, @02:59PM (#765209)

    thanks for editing the web to point to wikipedia ^_^