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At CES earlier this month, Intel finally demonstrated its first 10nm processor for desktops. The Ice Lake CPU is supposed to arrive by the end of 2019 after plenty of delays. Unfortunately, there may still be unforeseen complications, as industry rumours claim that Intel is struggling with implementing PCIe 4.0 support in the chipset.
Intel’s struggle to bring 10nm processors to the market has been well documented. During CES, there was some discussion around Ice Lake but very little was said about the accompanying chipset. We have heard through our industry sources (who will remain anonymous) that Intel is struggling in this area, with the upgrade to PCIe 4.0 being an issue in particular. There is some concern that this will end up causing more delays for Intel’s 10nm launch.
(Score: 0) by Anonymous Coward on Friday January 25 2019, @07:06PM (1 child)
i suppose the electron-on-copper-conductor-signal degrades over distance.
each transistor (or what they call them gates today) needs space and needs to "talk" to the next transistor.
for a bunch of transistors that only do I/O, like what pcie is for, that takes space for teh traces and thus they are spaced out and even
if laid out correctly will be visible as paths parallel to each other going from here to there inside the chip.
you can then take a ruler and measure the width of all these paths (think old printer cable).
the more I/O you want, the more of these path you need and the more distance and space it requires making the electron-on-copper-signal degradation worse.
now in, optic communication, there's something called multiplexing.
not to sound like a leader of the free world but this is a big secrit(sic):
you can take multiple fibre optic "conductors", feed them into a multiplexer, and this device combines all the feed-in optic-conductors into one. passively. no electricity needed. amazing.
so as you can guess, if they would integrate optics into the chip and the chip only and only for 1 mm (millimeter) distance, you can space the one bunch of I/O transistors on one side and connect them via a 1 mm optic multiplexer INISDE the CHIP only to the second bunch of I/O transistors on the right.
and you can keep adding and it will not increase the space required for the paths/traces as would happen if using electron-on-copper paths, since you can multiplex multiple inputs into one ... but only if using optics.
(Score: 2) by takyon on Saturday January 26 2019, @01:11AM
https://abcnews.go.com/Business/story?id=89816&page=1 [go.com]
good ol' 2004 news
What happened in 15 years?
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]