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posted by martyb on Saturday February 09 2019, @06:51PM   Printer-friendly
from the YMMV dept.

Wccftech reports that Micron plans to "introduce" NAND with 8 bits (1 byte) per cell:

Back in May of 2018, Micron introduced Quad-Level (QLC) NAND tech and, surprisingly, saw their stock tumble to pricing levels of ~$30 down from ~$60. This was the result of complex NAND pricing and supply/demand factors, not just the introduction of QLC, to be clear. I have just confirmed from multiple sources and stakeholders that Micron is intending to introduce their Octa-Level (OLC) NAND either in Q1 or latest by Q2 2019.

OLC NAND would have 28 (256) states and 28-1 (255) threshold voltages, compared to just 16 states for today's QLC NAND.

3D QLC NAND SSDs arrived on the market in 2018. QLC NAND has lower write endurance, estimated at 1,000 program/erase (PE) cycles, compared to 3,000 P/E cycles for triple-level cell (TLC) NAND, 10,000 P/E cycles for multi-level cell (MLC) NAND, and 100,000 P/E cycles for single-level cell NAND. This exceeds previous expectations of 1,000 P/E cycles for TLC NAND and 100 cycles for QLC NAND. Intel's SSD 660p drives using QLC NAND are rated for only about 0.1 drive writes per day for 5 years, or about 200 TB written on a 1 TB drive. Data retention is also reduced.

In 2013, it was reported that the U.S. Intelligence Advanced Research Projects Activity (IARPA) funded Crocus Technology development of 8-bits-per-cell Magnetic Logic Unit (MLU) memory, which would use two 4-bit layers:

Douglas Lee, VP for system strategy and corporate product development at Crocus, pointed out NAND and MRAM bits-per-cell limitations: "The current semiconductor non-volatile memory state-of-the-art is 3-4 bits per cell, as achieved in NAND flash memory, and is reaching the physical limits of floating gate memory technology. The current state-of-the-art in MRAM is only 1 bit per cell storage."


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  • (Score: 5, Informative) by KilroySmith on Saturday February 09 2019, @10:07PM (2 children)

    by KilroySmith (2113) on Saturday February 09 2019, @10:07PM (#798936)

    All flash devices have the "Cell" as the fundamental unit of storage, which is essentially a single Field Effect Transistor (FET). Let's assume that in the unprogrammed state, the FET is turned off. To program the device, some electrons are stored in the gate of the FET, which turns it on. To read it, you simply apply voltage and see if the cell conducts or not. Depending on how many electrons (how much charge) are stored in the gate, the FET has different resistances.

    M/T/Q/OLC refers to a technique of carefully controlling how many electrons are stored on the gate. For Single Level Cells (SLC), one bit is stored - there is either charge on the gate or not, and the reading electronics only have to look for on/off. For MLC, two bits of data are stored - four different amounts of charge are deposited in the gate, and when reading the electronics have to be able to differentiate four different resistances of the FET. For TLC, three bits are stored, 8 different amounts of charge are deposited, and for QLC four bits are stored with 16 different amounts of charge. OLC is 8 bits with 256 different amounts of charge.

    Vertical NAND flash simply refers to building layers of flash cells on top of each other. Old-style planar Nand flash just had an X-Y array of cells - think of a checkers board, or single-story hotel where every room is a cell. For V-Nand, we build vertically - 64-layer V-Nand is a 64 story hotel.

    So, S/M/T/Q/OLC defines how many bits are stored per cell, and V-Nand layers define how many cells are stacked on top of each other.

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  • (Score: 2) by fyngyrz on Sunday February 10 2019, @01:11AM (1 child)

    by fyngyrz (6567) on Sunday February 10 2019, @01:11AM (#798968) Journal

    OLC is 8 bits with 256 different amounts of charge.

    It's worth emphasizing that we can get the same 2D density with two layers of 4 bits / cell with 16 levels of charge each. TFS indicates this was at least attempted in 2013:

    In 2013, it was reported that the U.S. Intelligence Advanced Research Projects Activity (IARPA) funded Crocus Technology [theregister.co.uk] development of 8-bits-per-cell Magnetic Logic Unit (MLU) memory, which would use two 4-bit layers:

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    • (Score: 2) by takyon on Sunday February 10 2019, @01:54AM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Sunday February 10 2019, @01:54AM (#798972) Journal

      I don't know how applicable that is to NAND. It seems like a different kind of cell design using a shortcut that allows 8-bits-per-cell. I wanted to link it to show that something along these lines has been attempted, and quoted the text to show that 4-bits-per-cell was thought to be a limit for NAND (and it took years after that article for QLC to hit the market). Heck, something intermediate like 6-bits-per-cell should be easier, even if it doesn't give you that nice "one cell, one byte" design.

      If this news is real, I wouldn't be surprised if Micron also announces some dramatic technological development, like this one [ieee.org], that mitigates the likely downsides of OLC.

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