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posted by martyb on Friday April 05 2019, @07:21PM   Printer-friendly
from the contains-40%-of-your-RDA-of-acronyms dept.

Intel Launches Wi-Fi 6 AX200 Wireless Network Adapter

Intel has quietly launched its first Wi-Fi 6 (802.11ax) wireless network adapter, codenamed Cyclone Peak. The new WLAN adapter will deliver up to 2.4 Gbps network throughput when used with a compatible access point, but, like Wi-Fi 6 in general, its main advantage is that it will work better than existing adapters in RF-noisy environments where multiple Wi-Fi networks co-exist.

The Intel Wi-Fi 6 AX200 is a CNVi WLAN card that supports 802.11ax via 2x2 MU-MIMO antennas over the 2.4 GHz and 5 GHz bands. And never found too far from a Wi-Fi card, Intel's AX200 also supports Bluetooth 5.0.

[...] Intel's web-site says that the first Cyclone Peak wireless network adapter has been launched, so the device is available to makers of PCs. Depending on the order, the Intel Wi-Fi 6 AX200 costs Intel's customers from $10 to $17.

One of the commenters linked to this paper about 802.11be, a generation of Extremely High Throughput (EHT) Wi-Fi technology beyond 802.11ax that could offer a maximum throughput of at least 30 Gbps.

Previously: Netgear Introduces its First Wi-Fi 6 (802.11ax) Routers

Related: Wi-Fi Alliance Rebrands Wi-Fi Standards
Qualcomm Announces 802.11ay Wi-Fi Chips that Can Transmit 10 Gbps Within Line-of-Sight
Intel Promises "10nm" Chips by the End of 2019, and More


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  • (Score: 5, Interesting) by Snotnose on Friday April 05 2019, @10:53PM

    by Snotnose (1623) on Friday April 05 2019, @10:53PM (#825167)

    Ahhh, back in the day. circa '91/92, wrote an Ethernet driver for an Intel chip to be released RSN (we had advance knowledge). Wrote dummy code for the chip and got my driver working (this was not unusual back then). Chip arrives, serious lag issues in my code.

    Chip had a feature, you could chain together packets to be sent. Once you built a chain you pointed the chip to the first packet and set a master bit to make the chip process that chain. Each packet had a pointer to the next packet, and a bit that said whether or not the next packet was ready to send. Turned out, if you made packet and/or chain, and set the main bit, it took a good half second for the chip to see it and start transmitting the thing. But if you set the packet bit saying the next packet wasn't ready to go, then flipped it, you were golden.

    My solution? Every chain of packets had an empty packet at the end with the "next packet ready" flag set to "nope, not yet". When I had another bunch of packets ready to go I chained them up, set that mt packet's "next packet ready" flag to "yep, have at it", and off they went.

    What made it silver was when the chip came out my solution was in the official errata (uncredited of course). What made it golden was in '94, when I found Linux, I dug into the Ethernet device driver code and yep, there was my solution to the problem. Uncredited of course.

    --
    Why shouldn't we judge a book by it's cover? It's got the author, title, and a summary of what the book's about.
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