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Samsung Completes Development of 5nm EUV Process Technology
Samsung Foundry this week announced that it has completed development of its first-generation 5 nm fabrication process (previously dubbed 5LPE). The manufacturing technology uses extreme ultraviolet lithography (EUVL) and is set to provide significant performance, power, and area advantages when compared to Samsung's 7 nm process (known as 7LPP). Meanwhile, Samsung stresses that IP developed for 7LPP can be also used for chips to be made using 5LPE.
Samsung's 5 nm technology continues to use FinFET transistors, but with a new standard cell architecture as well as a mix of DUV and EUV step-and-scan systems. When compared to 7LPP, Samsung says that their 5LPE fabrication process will enable chip developers to reduce power consumption by 20% or improve performance by 10%. Furthermore, the company promises an increase in logic area efficiency of up to 25%.
One interesting technology that will eventually be on Samsung's roadmap: "gate-all-around" field effect transistors.
Meanwhile, TSMC has announced a new node, "6nm", which will allow for smaller die sizes than "7nm" with no improvements to performance or power consumption. It is also not better than the TSMC "7nm+" node, which will use extreme ultraviolet lithography:
TSMC this week unveiled its new 6 nm (CLN6FF, N6) manufacturing technology, which is set to deliver a considerably higher transistor density when compared to the company's 7 nm (CLN7FF, N7) fabrication process. An evolution of TSMC's 7nm node, N6 will continue to use the same design rules, making it easier for companies to get started on the new process. The technology will be used for risk production of chips starting Q1 2020.
TSMC states that their N6 fabrication technology offers 18% higher logic density when compared to the company's N7 process (1st Gen 7 nm, DUV-only), yet offers the same performance and power consumption. Furthermore, according to TSMC N6 'leverages new capabilities in extreme ultraviolet lithography (EUVL)' gained from N7+, but does not disclose how exactly it uses EUV for the particular technology. Meanwhile, N6 uses the same design rules as N7 and enables developers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will enable them to lower development costs. Essentially, N6 allows to shrink die sizes of designs developed using N7 design rules by around 15% while using the familiar IP for additional cost savings.
See table in article.
Previously: Samsung Discusses Foundry Plans Down to "3nm"
TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020
(Score: -1, Offtopic) by Anonymous Coward on Friday April 19 2019, @08:55PM (3 children)
Zzz ...
(Score: -1, Offtopic) by Anonymous Coward on Friday April 19 2019, @11:35PM (2 children)
Sorry, I will clarify my post: stories about process shrinks are the most boring stories in the world, like play by play coverage of paint drying.
It's my opinion, you may not agree with it, but it is on topic.
(Score: 2) by takyon on Saturday April 20 2019, @08:31AM (1 child)
That may be true, for you.
On the other hand, if another technology improves 5%, 10%, 20%, or 45% in some aspect, it could be front page news with billion or trillion dollar implications. We have gotten too used to the free lunch of the past and don't appreciate these "small" gains.
Maybe when 3D SoCs get commercialized in a few years/a decade you'll be less bored.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 1, Informative) by Anonymous Coward on Saturday April 20 2019, @09:21PM
I never said it wasn't a worthy achievement.
I just said it was boring. Accounting, as an example, is vital to keeping a business running. But stories about it all sound the same.