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Intel's 10th Gen, 10nm Ice Lake CPUs: everything you need to know
Intel has a lot to prove. 2018 marked the chipmaker's 50th anniversary, but it was also a year that shook the company to its core. It was the year that Intel lost its CEO, struggled with Spectre and Meltdown, and reportedly lost Apple's confidence as far as chips for future Macs are concerned. Above all, it was the year the world finally realized Intel processors had hit a wall, after yet another failure to shrink its circuits down to the "10 nanometer" process node.
But now, after years of delays, the company is about to bring its first real batch[*] of 10nm CPUs to the world. Today, the company is officially taking the wraps off its 10th Gen Intel Core processors, codename "Ice Lake," and revealing some of what they might be able to do for your next PC when they ship in June.
[*] 18% IPC improvement *loud coughing* compared "against the Skylake cores the company released nearly four years ago!"
Also at AnandTech and Tom's Hardware.
(Score: 3, Interesting) by takyon on Wednesday May 29 2019, @08:15PM (3 children)
Intel's "10nm" process is comparable to TSMC's "7nm". TSMC has better yields, and AMD's chiplet approach can handle defects better.
Intel will move to a chiplet approach and has demoed mixing process nodes. AMD uses "14nm" I/O die alongside "7nm" core chiplets. Intel demoed a chip that used "14nm" and "10nm" cores.
TSMC is only using extreme ultraviolet lithography (EUV) for some steps in its "7nm" process. "7nm+" and other processes will use more EUV, leading to lower defect rates.
TSMC has "5nm" coming. [tomshardware.com] TSMC, Samsung, and others are expect to move to a gate-all-around (GAA) design by "3nm", which should have improved tolerance to quantum tunneling/leakage.
https://semiengineering.com/transistor-options-beyond-3nm/ [semiengineering.com]
https://spectrum.ieee.org/nanoclast/semiconductors/devices/new-metalair-transistor-replaces-semiconductors [ieee.org]
As you can see, there are various options for continued scaling improvements.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by ikanreed on Wednesday May 29 2019, @08:45PM (2 children)
So I'm hearing "You were an idiot for taking internet commenters on a tech site 5 years ago as even remotely knowledgeable"
(Score: 0) by Anonymous Coward on Wednesday May 29 2019, @08:55PM
(Score: 2) by takyon on Wednesday May 29 2019, @09:05PM
I don't think "quantum interactions" really refers to the manufacturing defects. It's the manufacturing process which uses deep ultraviolet or soon extreme ultraviolet to create feature sizes that are smaller than the wavelength of the light used. So they have to use multiple patterning to handle that. But it will never be perfect.
You do have quantum tunneling that causes electrical leakage. But there is at least one transistor design [wikipedia.org] that can take advantage of that effect.
We are running into fundamental limits, but there are still a lot of ideas left in the bag to improve scaling and performance. Nanotube transistors, for example. The industry would prefer not to use new stuff if they can continue to tweak the old stuff.
I think there are credible ideas in the bagg which could lead to orders of magnitude of performance improvements.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]