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posted by martyb on Tuesday June 11 2019, @04:47AM   Printer-friendly
from the Good-Fast-AND-Cheap[er-than-Intel] dept.

At AMD's keynote at the 2019 Electronic Entertainment Expo (E3), AMD CEO Lisa Su announced three new "7nm" Navi GPUs and a new CPU.

The AMD Radeon RX 5700 XT will have 2560 stream processors (40 compute units) capable of 9.75 TFLOPs of FP32 performance, with 8 GB of 14 Gbps GDDR6 VRAM. The price is $449. The AMD RX 5700 cuts that down to 2304 SPs (36 CUs), 7.9 TFLOPs, at $379. There is a higher clocked "50th anniversary" version of the 5700 XT that offers up to 10.14 teraflops for $499. A teraflop on one of these new cards supposedly means better graphics performance than older Polaris-based GPUs:

Looking at these clockspeed values then, in terms of raw throughput the new card is expected to get between 9 TFLOPs and 9.75 TFLOPs of FP32 compute/shading throughput. This is a decent jump over the Polaris cards, but on the surface it doesn't look like a huge, generational jump, and this is where AMD's RDNA architecture comes in. AMD has made numerous optimizations to improve their GPU utilization – that is, how well they put those FLOPs to good use – so a teraflop on a 5700 card means more than it does on preceding AMD cards. Overall, AMD says that they're getting around 25% more work done per clock on the whole in gaming workloads. So raw specs can be deceiving.

The GPUs do not include real-time raytracing or variable rate pixel shading support. These may appear on a future generation of GPUs. Instead, AMD talked about support for DisplayPort 1.4 with Display Stream Compression, a contrast-enhancing post-processing filter, AMD Radeon Image Sharpening, and a Radeon Anti-lag feature to reduce input lag.

Towards the end of the presentation, AMD revealed the 16-core Ryzen 9 3950X, the company's fully-fledged Ryzen CPU with two 8-core "7nm" Zen 2 chiplets. Compared to the 12-core Ryzen 9 3900X CPU, the 3950X has a slightly higher boost clock and L2 cache, with the same 105 Watt TDP, for $749. This is the full lineup so far:

CPUCores / ThreadsFrequencyTDPPrice
Ryzen 9 3950X16 / 323.5 - 4.7 GHz105 W$749
Ryzen 9 3900X12 / 243.8 - 4.6 GHz105 W$499
Ryzen 7 3800X8 / 163.9 - 4.5 GHz105 W$399
Ryzen 7 3700X8 / 163.6 - 4.4 GHz65 W$329
Ryzen 5 3600X6 / 123.8 - 4.4 GHz95 W$249
Ryzen 5 36006 / 123.6 - 4.2 GHz65 W$199

Previously: AMD and Intel at Computex 2019: First Ryzen 3000-Series CPUs and Navi GPU Announced


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  • (Score: 2) by Rupert Pupnick on Tuesday June 11 2019, @01:11PM (4 children)

    by Rupert Pupnick (7277) on Tuesday June 11 2019, @01:11PM (#854183) Journal

    What type of chip packages? Can’t find anything in TFAs.

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    Karma-Bonus Modifier   +1  

    Total Score:   2  
  • (Score: 0) by Anonymous Coward on Tuesday June 11 2019, @02:22PM

    by Anonymous Coward on Tuesday June 11 2019, @02:22PM (#854207)

    🤦‍♀️

  • (Score: 2) by takyon on Wednesday June 12 2019, @01:40AM (2 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday June 12 2019, @01:40AM (#854467) Journal

    AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome [anandtech.com]

    The Zen 2 design paradigm, compared to the first generation of Zen, has changed significantly. The new platform and core implementation is designed around small 8-core chiplets built on TSMC’s 7nm manufacturing process, and measure around 74-80 square millimeters. On these chiplets are two groups of four-cores arranged in a ‘core complex’, or CCX, which contains those four cores and a set of L3 cache – the L3 cache is doubled for Zen 2 over Zen 1.

    Each full CPU, regardless of how many chiplets it has, is paired with a central IO die through Infinity Fabric links. The IO die acts as the central hub for all off-chip communications, as it houses all the PCIe lanes for the processor, as well as memory channels, and Infinity Fabric links to other chiplets or other CPUs. The IO die for the EPYC Rome processors is built on TSMC’s 14nm process, however the consumer processor IO dies (which are smaller and contain fewer features) are built on the Global Foundries 12nm process.

    The consumer processors, known as ‘Matisse’ or Ryzen 3rd Gen or Ryzen 3000-series, will be offered with up to two chiplets for sixteen cores. AMD is launching six versions of Matisse on July 7th, from six cores to sixteen cores. The six and eight-core processors have one chiplet, while above this the parts will have two chiplets, but in all cases the IO die is the same. This means that every Zen 2 based Ryzen 3000 processor will have access to 24 PCIe 4.0 lanes and dual channel memory. Based on the announcements today, the prices will range from $199 for the Ryzen 5 3600, up to [$750] for the sixteen core

    [...] The EPYC Rome processors, built on these Zen 2 chiplets, will have up to eight of them, enabling a platform that can support up to 64 cores. As with the consumer processors, no chiplet can communicate directly with each other – each chiplet will only connect directly to the central IO die. That IO die houses links for eight memory channels, and up to 128 lanes of PCIe 4.0 connectivity.

    Is that what you wanted to know?

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