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posted by martyb on Wednesday June 19 2019, @03:11PM   Printer-friendly
from the widest-band-yet dept.

PCI Express Bandwidth to Be Doubled Again: PCIe 6.0 Announced, Spec to Land in 2021

When the PCI Special Interest Group (PCI-SIG) first announced PCIe 4.0 a few years back, the group made it clear that they were not just going to make up for lost time after PCI 3.0, but that they were going to accelerate their development schedule to beat their old cadence. Since then the group has launched the final versions of the 4.0 and 5.0 specifications, and now with 5.0 only weeks old, the group is announcing today that they are already hard at work on the next version of the PCIe specification, PCIe 6.0. True to PCIe development iteration, the forthcoming standard will once again double the bandwidth of a PCIe slot – a x16 slot will now be able to hit a staggering 128GB/sec – with the group expecting to finalize the standard in 2021.

[...] PCIe 6.0, in turn, is easily the most important/most disruptive update to the PCIe standard since PCIe 3.0 almost a decade ago. To be sure, PCIe 6.0 remains backwards compatible with the 5 versions that have preceded it, and PCIe slots aren't going anywhere. But with PCIe 4.0 & 5.0 already resulting in very tight signal requirements that have resulted in ever shorter trace length limits, simply doubling the transfer rate yet again isn't necessarily the best way to go. Instead, the PCI-SIG is going to upend the signaling technology entirely, moving from the Non-Return-to-Zero (NRZ) tech used since the beginning, and to Pulse-Amplitude Modulation 4 (PAM4).

[...] PCIe 6.0 will be able to reach anywhere between ~8GB/sec for a x1 slot up to ~128GB/sec for a x16 slot (e.g. accelerator/video card). For comparison's sake, 8GB/sec is as much bandwidth as a PCIe 2.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.

Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
PCIe 5.0 Specification Finalized (yes, that was 3 weeks ago)


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  • (Score: 3, Interesting) by takyon on Wednesday June 19 2019, @03:37PM (2 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday June 19 2019, @03:37PM (#857476) Journal

    The price is expected to be high. Energy consumption may be higher. Physical limits are appearing.

    But with PCIe 4.0 & 5.0 already resulting in very tight signal requirements that have resulted in ever shorter trace length limits, simply doubling the transfer rate yet again isn’t necessarily the best way to go. Instead, the PCI-SIG is going to upend the signaling technology entirely, moving from the Non-Return-to-Zero (NRZ) tech used since the beginning, and to Pulse-Amplitude Modulation 4 (PAM4).

    [...] The tradeoff for using PAM4 is of course cost. Even with its greater bandwidth per Hz, PAM4 currently costs more to implement at pretty much every level, from the PHY to the physical layer. Which is why it hasn’t taken the world by storm, and why NRZ continues to be used elsewhere. The sheer mass deployment scale of PCIe will of course help a lot here – economies of scale still count for a lot – but it will be interesting to see where things stand in a few years once PCIe 6.0 is in the middle of ramping up.

    [...] As for end users and general availability of PCIe 6.0 products, while the PCI-SIG officially defers to the hardware vendors here, the launch cycles of PCIe 4.0 and 5.0 have been very similar, so PCIe 6.0 will likely follow in those same footsteps. 4.0, which was finalized in 2017, is just now showing up in mass market hardware in 2019, and meanwhile Intel has already committed to PCIe 5.0-capable CPUs in 2021. So we may see PCIe 6.0 hardware as soon as 2023, assuming development stays on track and hardware vendors move just as quickly to implement it as they have on earlier standards. Though for client/consumer use, it bears pointing out that with the rapid development pace for PCIe – and the higher costs that PAM4 will incur – just because the PCI-SIG develops 6.0 it doesn't mean it will show up in client decides any time soon; economics and bandwidth needs will drive that decision.

    I have no idea about laptops with 4.0. AMD's laptop chips lag behind desktop. AMD's new products support PCIe 4.0 although support may be limited to newer motherboards. Intel has said it will support PCIe 5.0 in 2021. We'll see about 6.0.

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  • (Score: 5, Insightful) by bob_super on Wednesday June 19 2019, @05:06PM (1 child)

    by bob_super (1357) on Wednesday June 19 2019, @05:06PM (#857520)

    It might be the opposite.
    4.0 is 16Gb/s/lane, which is pretty easy to do in a laptop where you control the traces. In a desktop with a slot, that's already trickier but not daunting. Do not buy 4.0 extension cards made by cheap morons who don't understand signal integrity, and plug your cards in properly, so the EQs can do they job.
    Power is irrelevant at 16G in 14 or less nm. You could get 128 transceivers cooking in an FPGA a while back at 22nm, and their power was meh compared to the rest of the logic processing that data.

    5.0 is 32Gb/s/lane. 4 years ago, I know first-hand that it was still hard to do on a fully-controlled PCB, because the weave of the material can even come into play at those frequencies. But it worked with careful design. I'd trust that most laptop manufacturers will have it figured out by now. Again, the discontinuity of adding the slot in a desktop, the longer traces, and the quality of the extension card you plug it, make me think lots of people will have issues. They might silently run at a lower speed (not sure how well their OS will tell them), or there might be lots of RMAs.
    A 16nm Xilinx FPGA power-estimates at 625mW per lane per end running 32G 128b/130b. Even counting an ASIC will cut that in half, that's a bit much for an ultrabook today. On the other hand, the thin-and-light laptops are not the ones sporting a discrete GPU with x16 connections, so limited use of 5.0 should be acceptable, and 7nm chips will cut the power down again.

    6.0, 64Gb/s/lane with PAM4 ? Probably limited to very few performance-critical lanes for a while, and the idea of slots is pretty scary.

    • (Score: 2) by takyon on Wednesday June 19 2019, @05:18PM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday June 19 2019, @05:18PM (#857526) Journal

      I just meant that AMD's laptop chips are released later than their desktop chips. Latest rumor [notebookcheck.net] is that it could come out in Q4 which is earlier than usual, but we still know nothing about core counts, use of chiplets, if it will use Vega or Navi graphics, etc.

      Nobody here will be seeing PCIe 6.0 anytime soon unless it's at work.

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