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PCI Express Bandwidth to Be Doubled Again: PCIe 6.0 Announced, Spec to Land in 2021
When the PCI Special Interest Group (PCI-SIG) first announced PCIe 4.0 a few years back, the group made it clear that they were not just going to make up for lost time after PCI 3.0, but that they were going to accelerate their development schedule to beat their old cadence. Since then the group has launched the final versions of the 4.0 and 5.0 specifications, and now with 5.0 only weeks old, the group is announcing today that they are already hard at work on the next version of the PCIe specification, PCIe 6.0. True to PCIe development iteration, the forthcoming standard will once again double the bandwidth of a PCIe slot – a x16 slot will now be able to hit a staggering 128GB/sec – with the group expecting to finalize the standard in 2021.
[...] PCIe 6.0, in turn, is easily the most important/most disruptive update to the PCIe standard since PCIe 3.0 almost a decade ago. To be sure, PCIe 6.0 remains backwards compatible with the 5 versions that have preceded it, and PCIe slots aren't going anywhere. But with PCIe 4.0 & 5.0 already resulting in very tight signal requirements that have resulted in ever shorter trace length limits, simply doubling the transfer rate yet again isn't necessarily the best way to go. Instead, the PCI-SIG is going to upend the signaling technology entirely, moving from the Non-Return-to-Zero (NRZ) tech used since the beginning, and to Pulse-Amplitude Modulation 4 (PAM4).
[...] PCIe 6.0 will be able to reach anywhere between ~8GB/sec for a x1 slot up to ~128GB/sec for a x16 slot (e.g. accelerator/video card). For comparison's sake, 8GB/sec is as much bandwidth as a PCIe 2.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
PCIe 5.0 Specification Finalized (yes, that was 3 weeks ago)
(Score: 4, Informative) by Rupert Pupnick on Wednesday June 19 2019, @05:08PM
Typical PCB losses go up in proportion to the sum of both f (dielectric loss) and sqrt(f) (skin effect) terms, so doubling the operating frequency more than doubles the loss per unit distance, which after a while gets truly oppressive for NRZ. Highest signaling rate I’ve seen (2017, in case you were wondering) for electrical interfaces that service OTN is about 28 Gb/s per differential pair. To get to 56 Gb/s these standards are also going to PAM4.
When you use 4 level signaling, you need a better signal to noise ratio to get the same BER performance. This will result in even more prescriptive routing rules for designers that will undoubtedly use up more board resources. Also, since noise sensitivity is going up, designers may be in for some surprises because real PCB noise simulations are pretty much non existent.
Probably a significant cost/yield impact on the silicon, too. Receiver complexity is significantly higher than a regular old NRZ macro.