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posted by Fnord666 on Wednesday July 03 2019, @07:52PM   Printer-friendly
from the moore-of-a-guideline dept.

Intel's Senior Vice President Jim Keller (who previously helped to design AMD's K8 and Zen microarchitectures) gave a talk at the Silicon 100 Summit that promised continued pursuit of transistor scaling gains, including a roughly 50x increase in gate density:

Intel's New Chip Wizard Has a Plan to Bring Back the Magic (archive)

In 2016, a biennial report that had long served as an industry-wide pledge to sustain Moore's law gave up and switched to other ways of defining progress. Analysts and media—even some semiconductor CEOs—have written Moore's law's obituary in countless ways. Keller doesn't agree. "The working title for this talk was 'Moore's law is not dead but if you think so you're stupid,'" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore's law.

[...] Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. "That's basically already working," he said.

The ~50x gate density claim combines ~3x density from additional pitch scaling (from "10nm"), ~2x from nanowires, another ~2x from stacked nanowires, ~2x from wafer-to-wafer stacking, and ~2x from die-to-wafer stacking.

Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed
Intel's "Tick-Tock" is Now More Like "Process-Architecture-Optimization"
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Another Step Toward the End of Moore's Law


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  • (Score: 3, Interesting) by takyon on Wednesday July 03 2019, @09:12PM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday July 03 2019, @09:12PM (#862908) Journal

    I'm not sure I see it as a plan for big winning. More like a plan for keeping up with the rest of the pack.

    TSMC "5nm" [soylentnews.org] = 45% area reduction = 1.8x transistor density. Combine that with a "3nm" and maybe smaller nodes, and they should be able to get at least 3x from "pitch scaling", maybe more.

    TSMC's wafer-on-wafer plans [soylentnews.org] cover the latter portion of the improvements.

    There are other tricks left in the bag lab that could reduce power consumption, increase frequency, and allow vertical scaling (which probably isn't feasible with how hot chips are running today).

    Intel's Foveros, Big/Small (like ARM's big.LITTLE/DynamIQ), and DRAM stacking/integration plans [soylentnews.org] will be more interesting in the long run than some scaling innovations that are going to be industry standard.

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