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Alibaba Crafts A 16-Core RISC-V Chip @ 2.5GHz
Alibaba this week announced a RISC-V 64-bit processor comprised of 16 cores at 2.5GHz. The Chinese RISC-V CPU is fabbed at 12nm and this RISC-V processor supports out of order execution. This Alibaba design achieves a 7.1 Coremark/MHz rating, a great deal faster than any other publicly announced RISC-V processor. It's still not as fast as say the newest AMD Ryzen 9 or Intel Core i7/i9 parts, but it's certainly much better than all of the other RISC-V processors/SoCs we've seen announced to date. Unfortunately additional details on this Alibaba design are light.
Also at Tom's Hardware.
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(Score: 3, Interesting) by fyngyrz on Sunday July 28 2019, @03:54PM (2 children)
I'm still dreaming of someone doing a chip with something like the integer side of the 6809 expanded to 64 bits and the associated shitload of registers those bits in an instruction word would enable — the addressing modes alone were bloody fabulous. Add a robust FPU and memory management, cache, some sweet bit manipulation, memory movement, and atomic semaphore-like operations, and you'd have one hell of a CPU.
The Intel mess is still... a mess. RISC is still too... RISC. I pine for an instruction set that is both powerful and highly, or even better perfectly, applicable across all CPU registers.
But oh well. We're too deep in this hole to dig ourselves out, methinks.
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(Score: 2) by shortscreen on Monday July 29 2019, @12:35AM (1 child)
I find it difficult to make up my mind about this topic. From the standpoint of programming in assembly, I'd be thinking about something along the lines of what you describe. A clean design without decades of vestigal junk in it, more on the CISC side, but with plenty of general purpose registers. (Did you ever read about the NEC V60? That might be in the ballpark.) But from the standpoint of using a compiler, maybe I can overlook whatever bizarre voodoo the chip designers and compiler writers came up with to increase throughput, as long as it works. (Huh? Did somebody say meltdown?) And then there's looking at it from the standpoint of actually writing a compiler. Now all those registers aren't looking so great, because the more registers there are, the smarter the compiler will have to be to actually make use of them. So maybe I'll just trim those out and save some bits in the instruction word. Speaking of which, writing a compiler would also be easier without having to deal with a thousand different instruction encodings and operand types and prefixes. And passing parameters on the stack is so easy let's keep doing it that way...
(Score: 2) by fyngyrz on Monday July 29 2019, @09:18PM
...kind of depends on how you write the compiler. The more registers with the same functionality there are, the more types of operations and operands can be register-resident without having to resort to stack-flippery.
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