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posted by Fnord666 on Friday August 16 2019, @11:59AM   Printer-friendly
from the a-what? dept.

TSMC Shows Colossal Interposer, Says Moore's Law Still Alive

In the company's first blog post, TSMC has stated that Moore's Law is still alive and well, despite the zeitgeist of recent times being the reverse. The company also showed a colossal 2500mm2 interposer that includes eight HBM memory chips and two big processors.

Godfrey Cheng, TSMC's new head of global marketing, wrote the blog post. He notes that Moore's Law is not about performance, but about transistor density. While performance traditionally improved by increasing the clock speed and architecture, today it is more often improved by increasing parallelization, and hence requires increases in chip size. This enhances the importance of transistor density because chip cost is directly proportional to its area.

[...] "one possible future of great density improvements is to allow the stacking of multiple layers of transistors in something we call Monolithic 3D Integrated Circuits. You could add a CPU on top of a GPU on top of an AI Edge engine with layers of memory in between. Moore's Law is not dead, there are many different paths to continue to increase density."

[...] [System-technology co-optimization (STCO)] is done through advanced packaging, for which TSMC supports silicon-based interposers and fan-out-based chiplet integration. It also has techniques to stack chips on wafers, or stack wafers on top of other wafers. As one such example, TSMC showed a nearly-2500mm2 silicon interposer – the world's largest – on top of which two 600mm2 processors are placed and eight 75mm2 HBM memory chips, which makes for 1800mm2 of compute and memory silicon on top of the interposer-based package, well over two times the conventional reticle size limit.

Related: Dual-Wafer Packaging (Wafer-on-Wafer) Could Double CPU/GPU Performance
Another Step Toward the End of Moore's Law
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan


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  • (Score: 2) by takyon on Friday August 16 2019, @04:42PM (2 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday August 16 2019, @04:42PM (#881162) Journal

    We can already see the next steps with clarity. From the TSMC blog post [tsmc.com]:

    To feed modern fast CPUs, GPUs and dedicated AI Processors, it is critical to provide memory that is both physically closer to the cores that are requesting the data for improved latency, in addition to supplying a higher bandwidth of data for the cores to process. This is what device level density provides. When memory is collocated closer to the logic cores, the system achieves lower latency, lower power consumption and higher overall performance.

    [...] Advanced packaging today brings memory close to the logic. Typically, logic cores are fed through standalone memory chips through interfaces such as DDR or GDDR. The physical distance between the memory device and the logic cores limit performance through increased latency. Bandwidth is also limited with discrete memory as they only offer limited interface width. Additionally, power consumption for discrete logic and memory also govern a device's overall performance, especially in applications such as smartphones or IOT devices as there is limited ability to dissipate the thermal energy radiated by discrete devices.

    [...] Tight integration of logic cores with memory through advanced packaging techniques are already available today from TSMC. The line between a semiconductor and a system solution is blurry as the new advanced packaging techniques are silicon wafer based. TSMC has pioneered advanced packaging techniques that allow our customers to deliver a complete system with a silicon-based interposer or fan-out-based chiplet integration. We also have advanced packaging techniques that allow us to stack chips on wafers or stack wafer on wafer prior to integration into packaged modules. These advanced packaging techniques allow TSMC customers to deliver much higher density and more performance. We will continue to drive innovation in advanced packaging technologies.

    Intel and AMD are working on 2.5D/3D designs that stack memory near or on top of the CPU, but the real winner is going to be:

    DARPA's 3DSoC Becoming a Reality [soylentnews.org]

    With that tight integration of memory and cores in layers, we could see CPUs that outperform today's flagship Intel/AMD chips, but with the power consumption of a smartphone SoC or RasPi Zero. That's before you take into account transistor advances [soylentnews.org]. The memory amounts of the very first 3DSoCs will probably be around 4 GB to 8 GB. If we can eventually use dense non-volatile universal memory in the same place, maybe we can have 1 TB or more there instead, and do all computing in memory.

    We are going to see performance increases in the orders of magnitude. Single-board computers with 3DSoCs will meet the computing needs of the vast majority of users. We'll still see a trend towards embarrassingly parallel core/thread counts (64-core Threadripper, anyone?), but those who actually need that will probably be pushing zettaflops.

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  • (Score: 1) by ChrisMaple on Sunday August 18 2019, @12:25AM (1 child)

    by ChrisMaple (6964) on Sunday August 18 2019, @12:25AM (#881612)

    I have doubts about those transistor advances, specifically the cited Air Channel Transistor with a performance boost of ten thousand. Field emission devices tend to erode at high currents, and high currents are necessary for the high speeds that charge interconnect capacitances -- and interconnect capacitances don't go away even when the transistors improve. The article claims that there's no power dissipation in the transistors because there's no material to get in the way of the electrons: that's blatantly false; an electron going through a potential (voltage) change always and inescapably involves power.

    Perhaps some day Air Channel Transistors will be a commercial reality in integrated circuits, but I'd be greatly surprised if they caused as much as a 3X speed improvement.

    • (Score: 2) by takyon on Sunday August 18 2019, @12:43AM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Sunday August 18 2019, @12:43AM (#881617) Journal

      It's just one of a number of advancements that will be competing to leave the lab and enter the fab. Some of them will never be practical, but multiple could succeed.

      However, the concept of moving logic ever closer to memory is a done deal, and impossible to ignore.

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