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posted by janrinok on Tuesday September 03 2019, @08:21PM   Printer-friendly
from the everything-is-tubes dept.

MIT Engineers Build 15,000-Transistor Carbon Nanotube RISC-V Chip

Engineers from the MIT and Analog Devices have created the most complex chip design yet that uses transistors made of carbon nanotubes instead of silicon. The chip was manufactured using new technologies proven to work in a commercial chip-manufacturing facility.

The researchers seem to have chosen the RISC-V instruction set architecture (ISA) for the design of the chip, presumably due to the open source nature that didn't require hassling with licensing restrictions and costs. The RISC-V processor handles 32-bit instructions and does 16-bit memory addressing. The chip is not meant to be used in mainstream devices quite yet, but it's a strong proof of concept that can already run "hello world"-type applications.

One advantage transistors made out of carbon nanotubes have over silicon transistors is that they can be manufactured in multiple layers, allowing for very dense 3D chip designs. DARPA also believes that carbon nanotubes may allow for the manufacturing of future 3D chips that have performance similar or better than silicon chips, but they can also be manufactured for much lower costs.

Also at IEEE.

Modern microprocessor built from complementary carbon nanotube transistors (DOI: 10.1038/s41586-019-1493-8) (DX)


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  • (Score: 2) by RamiK on Wednesday September 04 2019, @01:22AM (6 children)

    by RamiK (1813) on Wednesday September 04 2019, @01:22AM (#889340)

    [_] Redefine "reduced" to mean what Americans expect

    This can be argued as revisionist, but RISC doesn't mean there are fewer instructions. It means you have explicit load/store instructions so the other instructions are reduced to just computations as opposed to CISC where the load/store are built-in the instructions.

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  • (Score: 2) by stormwyrm on Wednesday September 04 2019, @09:00AM (5 children)

    by stormwyrm (717) on Wednesday September 04 2019, @09:00AM (#889444) Journal

    Yes, RISC doesn't generally mean less instructions, but simpler instructions. The thinking that motivated RISC architectures was that the CISC processors like the 80x86 had an inordinately large amount of silicon allocated just to decode instructions (the microcode). So RISC design philosophy was to simplify the instruction set, so the instructions become more regular and primitive by definition. This means takes more of them to do the same thing, but this is made up for by making instruction decoding much simpler and faster, and more efficient use can be made of the various processing units much more easily. For example, on the 80x86 you can simply say "ADD Value, 10", which will add 10 to the memory location pointed to by Value. On the other hand, on a typical RISC architecture like the i860 you'd have to do something like this:

      ORH    Value_HI,r0,r3  ; Place upper and lower 16
      OR     Value_LO,r3,r3  ;  bits of VALUE addr in r3
      LD.L   0 (r3),r4       ; Load [0+r3] into r4
      ADDS   10,r4,r4        ; r4 = r4 + 10
      ST.L   r4,0 (r3)       ;  Store r4 in [0+r3]

    I imagine that the equivalent RISC V code is not far off.

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    Numquam ponenda est pluralitas sine necessitate.
    • (Score: 2) by DannyB on Wednesday September 04 2019, @01:48PM (3 children)

      by DannyB (5839) Subscriber Badge on Wednesday September 04 2019, @01:48PM (#889516) Journal

      I'm not saying I agree with this article [blackhole12.com], but its first paragraph points out a single instruction that is pretty complex.

      People still call ARM a “RISC” architecture despite ARMv8.3-A adding a FJCVTZS instruction [wikipedia.org], which is “Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero”. Reduced instruction set, my ass.

      As the 2nd paragraph points out, one of the big problems is that, for some reason, the speed of light isn't getting any faster. Something I think that congress should consider fixing. Maybe an international effort.

      Back in the day, I found the x86 a PITA to code for. The Motorola 68000 (used on Mac) was a pleasure to code for. I similarly suspect I would find ARM a pleasure to use, but haven't tried. Probably getting too old at this point.

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      People today are educated enough to repeat what they are taught but not to question what they are taught.
      • (Score: 3, Informative) by stormwyrm on Wednesday September 04 2019, @05:24PM (2 children)

        by stormwyrm (717) on Wednesday September 04 2019, @05:24PM (#889596) Journal

        Ah, but how many memory cycles does FJCVTZS use when executed? I imagine it does its black magic only on registers, so it's essentially 1, just the single fetch of the instruction itself, so despite its specialised nature, it is effectively a rather simple instruction as far as the architecture is concerned. It is in principle no different from, say, the instructions that compute trigonometric functions on floating point registers. Oddball specialised instructions like FJCVTZS do not make an architecture into a CISC. Contrast that with the x86 ADD Value,10 instruction, which in its microcode has to make at least four memory accesses, one to get the instruction, another its operands, then the contents of the pointer to Value, and finally to store the sum. That is what is meant by the "complex" in CISC. It has nothing to with what the instructions actually do, but rather with how they do them.

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        Numquam ponenda est pluralitas sine necessitate.
        • (Score: 2) by DannyB on Wednesday September 04 2019, @06:03PM

          by DannyB (5839) Subscriber Badge on Wednesday September 04 2019, @06:03PM (#889612) Journal

          I get that and you make a good point.

          There still remains the question of which glows more brightly which should be the subject of further research.

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          People today are educated enough to repeat what they are taught but not to question what they are taught.
        • (Score: 2) by RamiK on Wednesday September 04 2019, @06:04PM

          by RamiK (1813) on Wednesday September 04 2019, @06:04PM (#889613)

          how many memory cycles does FJCVTZS use when executed?...

          Exactly. I would also add a caveat about SIMD vs. vector instructions in lieu of https://www.sigarch.org/simd-instructions-considered-harmful/ [sigarch.org] : You can get a lot of computations done with a single instruction and the compiler CAN take good advantage of those in many places. I admit it's not as good as the Mill is but the Mill doesn't really cover most of the embedded range so RISC-V will always have a nice and stable niche.

          Overall, RISC-V has its room and is hardly bloated.

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    • (Score: 2) by DannyB on Wednesday September 04 2019, @02:00PM

      by DannyB (5839) Subscriber Badge on Wednesday September 04 2019, @02:00PM (#889524) Journal

      Also, I do not intend to confuse RISC-V with ARM. Criticisms of either may not apply to the other.

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      People today are educated enough to repeat what they are taught but not to question what they are taught.