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MIT Engineers Build 15,000-Transistor Carbon Nanotube RISC-V Chip
Engineers from the MIT and Analog Devices have created the most complex chip design yet that uses transistors made of carbon nanotubes instead of silicon. The chip was manufactured using new technologies proven to work in a commercial chip-manufacturing facility.
The researchers seem to have chosen the RISC-V instruction set architecture (ISA) for the design of the chip, presumably due to the open source nature that didn't require hassling with licensing restrictions and costs. The RISC-V processor handles 32-bit instructions and does 16-bit memory addressing. The chip is not meant to be used in mainstream devices quite yet, but it's a strong proof of concept that can already run "hello world"-type applications.
One advantage transistors made out of carbon nanotubes have over silicon transistors is that they can be manufactured in multiple layers, allowing for very dense 3D chip designs. DARPA also believes that carbon nanotubes may allow for the manufacturing of future 3D chips that have performance similar or better than silicon chips, but they can also be manufactured for much lower costs.
Also at IEEE.
Modern microprocessor built from complementary carbon nanotube transistors (DOI: 10.1038/s41586-019-1493-8) (DX)
(Score: 3, Informative) by stormwyrm on Wednesday September 04 2019, @05:24PM (2 children)
Ah, but how many memory cycles does FJCVTZS use when executed? I imagine it does its black magic only on registers, so it's essentially 1, just the single fetch of the instruction itself, so despite its specialised nature, it is effectively a rather simple instruction as far as the architecture is concerned. It is in principle no different from, say, the instructions that compute trigonometric functions on floating point registers. Oddball specialised instructions like FJCVTZS do not make an architecture into a CISC. Contrast that with the x86 ADD Value,10 instruction, which in its microcode has to make at least four memory accesses, one to get the instruction, another its operands, then the contents of the pointer to Value, and finally to store the sum. That is what is meant by the "complex" in CISC. It has nothing to with what the instructions actually do, but rather with how they do them.
Numquam ponenda est pluralitas sine necessitate.
(Score: 2) by DannyB on Wednesday September 04 2019, @06:03PM
I get that and you make a good point.
There still remains the question of which glows more brightly which should be the subject of further research.
What doesn't kill me makes me weaker for next time.
(Score: 2) by RamiK on Wednesday September 04 2019, @06:04PM
Exactly. I would also add a caveat about SIMD vs. vector instructions in lieu of https://www.sigarch.org/simd-instructions-considered-harmful/ [sigarch.org] : You can get a lot of computations done with a single instruction and the compiler CAN take good advantage of those in many places. I admit it's not as good as the Mill is but the Mill doesn't really cover most of the embedded range so RISC-V will always have a nice and stable niche.
Overall, RISC-V has its room and is hardly bloated.
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