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from the an-organization-of-very-special-registers dept.
http://www.righto.com/2019/10/how-special-register-groups-invaded.html
Half a century ago, the puzzling phrase "special register groups" started showing up in definitions of "CPU", and it is still there. In this blog post, I uncover how special register groups went from an obscure feature in the Honeywell 800 mainframe to appearing in the Washington Post.
While researching old computers, I found a strange definition of "Central Processing Unit" that keeps appearing in different sources. From a book reprinted in 2017:1
"Central Processor Unit (CPU)—Part of a computer system which contains the main storage, arithmetic unit and special register groups. It performs arithmetic operations, controls instruction processing and provides timing signals."
At first glance, this definition seems okay, but a few moments thought reveals some problems. Storage is not part of the CPU. But more puzzling, what are special register groups? A CPU has registers, but "special register groups" is not a normal phrase.
It turns out that this definition has been used extensively for over half a century, even though it doesn't make sense, copied and modified from one source to another. Special register groups were a feature in the Honeywell 800 mainframe computer, introduced in 1959. Although this computer is long-forgotten, its impact inexplicably remains in many glossaries. The Honeywell 800 allowed eight programs to run on a single processor, switching between programs after every instruction.3 To support this, each program had a "special register group" in hardware, its own separate group of 32 registers (program counter, general-purpose registers, index registers, etc.).
(Score: 2) by takyon on Thursday October 24 2019, @09:36PM (3 children)
They'll reduce heat by running it as low as 0.5 Watts.
There's a big energy savings from moving the CPU cores to within nanometers of the memory.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by RamiK on Thursday October 24 2019, @11:01PM (2 children)
But if they have the room for it, they could just as well stick conventional cache in there as well... So, you have to wonder why didn't they just go with a super-sized die like those guys?
Regardless, I'm not saying it's not going to happen. But having waited for Intel to deliver a single node reduction for this long... Well, something tells me not to hold my breath for any of these "just around the corner" fabrication methods.
compiling...
(Score: 2) by c0lo on Friday October 25 2019, @04:22AM (1 child)
One error in a single gate and your very complex chip lands in the rejected bin.
How lucky or masterful you need to be to end with a good enough number of chips that pass the tests?
https://www.youtube.com/watch?v=aoFiw2jMy-0 https://soylentnews.org/~MichaelDavidCrawford
(Score: 2) by RamiK on Friday October 25 2019, @12:02PM
High cost big silicon dies like Intel's and IBM's are designed so it's either possible to fuse out defective logic blocks and sell the chips as reduced features / lower performance models or also place redundancies that you can fuse on and off.
Well, it's a gross simplification of yield equations and design choices, but there's ways around production defects for sure.
compiling...