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from the when-will-we-see-a-Raspberry^W-Ryzen-pi? dept.
AMD Launches Ultra-Low-Power Ryzen Embedded APUs: Starting at 6W
While it doesn't get the same attention as their high-profile mobile, desktop, or server CPU offerings, AMD's embedded division is an important fourth platform for the chipmaker. To that end, this week the company is revealing its lowest-power Ryzen processors ever, with a new series of embedded chips that are designed for use in ultra-compact commercial and industrial systems.
The chips in question are the AMD Ryzen Embedded R1102G and the AMD Ryzen Embedded R1305G SoCs. These parts feature a 6 W or a configurable 8 W - 10 W TDP, respectively. Both SoCs feature two Zen cores with or without simultaneous multithreading, AMD Radeon Vega 3 graphics, 1 MB L2 cache, 4 MB L3 cache, a single channel or a dual-channel memory controller, and two 10 GbE ports.
[...] Both ultra-low-power AMD Ryzen Embedded APUs will be available for the next 10 years, meaning availability will stretch all the way till 2030.
AMD Ryzen Embedded R1000 Series
(Score: 1, Interesting) by Anonymous Coward on Saturday February 29 2020, @07:11PM
For the same process and same clockrate, AMD has not been hotter except for certain 'enthusiast' models of processors (primarily the hammer athlon64's and some of their early overclocked x86 (386/486/586) second source chips.) Having said that, they have been 1-2 generations behind in process technology basically forever and until they integrated a thermal probe on-die, they were much more prone to thermal runaway than Intel in the case of overclocking or fan failures (which may have been responsible for some of that misttated fact.) Intel's chips have be far more prone to thermal throttling in actual practice in my experience, the mid to late pentium 4 era being the worst when the memory bus got fast enough to keep the chip saturated and those stupid plastic pushpins made it difficult or impossible to have the heatsink evenly and securely fastened against the heat spreader across all thermal ranges. While the Core 2 and later chips much improved that, it was mostly by halving the clock rate and dramatically increasing the cache size, which gave more opportunities to microsleep while pulling data from memory into cache.