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Today, we've decided to revisit some of the worst CPUs ever built. To make it on to this list, a CPU needed to be fundamentally broken, as opposed to simply being poorly positioned or slower than expected. The annals of history are already stuffed with mediocre products that didn't quite meet expectations but weren't truly bad.
Note: Plenty of people will bring up the Pentium FDIV bug here, but the reason we didn't include it is simple: Despite being an enormous marketing failure for Intel and a huge expense, the actual bug was tiny. It impacted no one who wasn't already doing scientific computing and the scale and scope of the problem in technical terms was never estimated to be much of anything. The incident is recalled today more for the disastrous way Intel handled it than for any overarching problem in the Pentium micro-architecture.
We also include a few dishonourable mentions. These chips may not be the worst of the worst, but they ran into serious problems or failed to address key market segments. With that, here's our list of the worst CPUs ever made.
- Intel Itanium
- Intel Pentium 4 (Prescott)
- AMD Bulldozer
- Cyrix 6×86
- Cyrix MediaGX
- Texas Instruments TMS9900
Which CPUs make up your list of Worst CPUs Ever Made?
(Score: 2) by maxwell demon on Thursday April 23 2020, @07:10PM (3 children)
My guess would be that the shorter context switching time was more than offset by longer time to do calculations. As far as I remember, main memory accesses have always been slower than CPU register accesses. Thus I would be surprised if the TMS9900 memory "registers" were not causing it to be much slower than chips with on-chip registers.
The Tao of math: The numbers you can count are not the real numbers.
(Score: 2) by RS3 on Friday April 24 2020, @12:27AM (2 children)
Absolutely agree. After posting, I did some more reading, looked at some pinouts, saw the 3 (???) clock phase inputs, and remember how horribly slow memory access was in those days. To be fair, it's still many clock cycles, but we have DDR4, "quad pumped" bus, etc. I wonder if the TI engineers were hoping for faster RAM or something?
Either way, it was a tradeoff between faster context switches versus faster register operations. We all know who won out!
(Score: 1, Insightful) by Anonymous Coward on Friday April 24 2020, @07:35AM (1 child)
More likely that their fab couldn't get the required transistor density to fit everything, so something had to give. CPUs that fit on a single chip were still a pretty new thing in those days.
(Score: 2) by RS3 on Friday April 24 2020, @03:08PM
Great point. And, especially in those days, chip yields (usable ICs) were low, and the bigger the die, statistically the fewer good ones you'll get. And they didn't have the PGA and 4-sided PLCC and BGA packages that they developed for the LSI in the 80s. So making bigger chips would have cost much more and nobody would have bought.
Which brings up the memory that there were some multi-package microprocessors, and I forget which ones did that, but it was 2 or 3 chips, and they were not popular.