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posted by martyb on Thursday April 23 2020, @12:33PM   Printer-friendly
from the Sorry-about-that-boss! dept.

Worst CPUs:

Today, we've decided to revisit some of the worst CPUs ever built. To make it on to this list, a CPU needed to be fundamentally broken, as opposed to simply being poorly positioned or slower than expected. The annals of history are already stuffed with mediocre products that didn't quite meet expectations but weren't truly bad.

Note: Plenty of people will bring up the Pentium FDIV bug here, but the reason we didn't include it is simple: Despite being an enormous marketing failure for Intel and a huge expense, the actual bug was tiny. It impacted no one who wasn't already doing scientific computing and the scale and scope of the problem in technical terms was never estimated to be much of anything. The incident is recalled today more for the disastrous way Intel handled it than for any overarching problem in the Pentium micro-architecture.

We also include a few dishonourable mentions. These chips may not be the worst of the worst, but they ran into serious problems or failed to address key market segments. With that, here's our list of the worst CPUs ever made.

  1. Intel Itanium
  2. Intel Pentium 4 (Prescott)
  3. AMD Bulldozer
  4. Cyrix 6×86
  5. Cyrix MediaGX
  6. Texas Instruments TMS9900

Which CPUs make up your list of Worst CPUs Ever Made?


Original Submission

 
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  • (Score: 3, Interesting) by maxwell demon on Thursday April 23 2020, @07:36PM (3 children)

    by maxwell demon (1608) on Thursday April 23 2020, @07:36PM (#986174) Journal

    The reason for the BCD instructions in the 8086/8088 (as well as some other special instructions like LAHF/SAHF) is the goal of a straightforward mechanical translation of 8080 code into 8086 code. Therefore it was essential that all 8080 functionality was either directly available on the 8086 (such as with BCD arithmetic) or there were fixed instruction sequences to achieve that (the 8080 always pushed the 8-bit accumulator together with the flags; this could be emulated on the 8086 with the LAHF/PUSH AX and POPAX/SAHF sequences). Also AFAIK the segmented architecture was for this reason: That way you could use 16-bit addresses in your programs (just as on the 8080), despite being able to access more memory in total.

    --
    The Tao of math: The numbers you can count are not the real numbers.
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  • (Score: 2) by RS3 on Friday April 24 2020, @01:09AM (2 children)

    by RS3 (6367) on Friday April 24 2020, @01:09AM (#986319)

    I was thinking the BCD stuff was also for very simple systems that had 7-segment displays. Maybe? No?

    • (Score: 2) by maxwell demon on Friday April 24 2020, @06:57AM (1 child)

      by maxwell demon (1608) on Friday April 24 2020, @06:57AM (#986412) Journal

      In the 8080, that may well be. In the 8086, the question wouldn't arise, since the compatibility restraints meant the support would have to be there anyway.

      If Intel expected the 8086 (or the 8088) to be used in such systems, I have no idea. I would have expected embedded systems of that time to still go with 8 bit CPUs.

      --
      The Tao of math: The numbers you can count are not the real numbers.
      • (Score: 2) by RS3 on Friday April 24 2020, @03:19PM

        by RS3 (6367) on Friday April 24 2020, @03:19PM (#986503)

        Yes, I have to agree, and the 8085 filled that market nicely. You probably know on the 86/88, the address and data were multiplexed pins, so you needed several glue logic chips just to do anything with the micro. Maybe that was common then? Too lazy to look up other chip pinouts... Look how good we have it now with RAM and ROM and FLASH inside the micro.